数据搜索系统,热门电子元器件搜索
  Chinese  ▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

EPM7064S 数据表(PDF) 49 Page - Altera Corporation

部件名 EPM7064S
功能描述  Programmable Logic Device Family
Download  66 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPM7064S 数据表(HTML) 49 Page - Altera Corporation

Back Button EPM7064S Datasheet HTML 45Page - Altera Corporation EPM7064S Datasheet HTML 46Page - Altera Corporation EPM7064S Datasheet HTML 47Page - Altera Corporation EPM7064S Datasheet HTML 48Page - Altera Corporation EPM7064S Datasheet HTML 49Page - Altera Corporation EPM7064S Datasheet HTML 50Page - Altera Corporation EPM7064S Datasheet HTML 51Page - Altera Corporation EPM7064S Datasheet HTML 52Page - Altera Corporation EPM7064S Datasheet HTML 53Page - Altera Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 49 / 66 page
background image
Altera Corporation
49
MAX 7000 Programmable Logic Device Family Data Sheet
tAH
Array clock hold time
1.8
3.0
4.0
ns
tACO1
Array clock to output delay
C1 = 35 pF
7.8
10.0
15.0
ns
tACH
Array clock high time
3.0
4.0
6.0
ns
tACL
Array clock low time
3.0
4.0
6.0
ns
tCPPW
Minimum pulse width for clear
and preset
(2)
3.0
4.0
6.0
ns
tODH
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
ns
tCNT
Minimum global clock period
8.0
10.0
13.0
ns
fCNT
Maximum internal global clock
frequency
(4)
125.0
100.0
76.9
MHz
tACNT
Minimum array clock period
8.0
10.0
13.0
ns
fACNT
Maximum internal array clock
frequency
(4)
125.0
100.0
76.9
MHz
fMAX
Maximum clock frequency
(5)
166.7
125.0
100.0
MHz
Table 36. EPM7192S Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
-15
Min
Max
Min
Max
Min
Max
tIN
Input pad and buffer delay
0.3
0.5
2.0
ns
tIO
I/O input pad and buffer delay
0.3
0.5
2.0
ns
tFIN
Fast input delay
3.2
1.0
2.0
ns
tSEXP
Shared expander delay
4.2
5.0
8.0
ns
tPEXP
Parallel expander delay
1.2
0.8
1.0
ns
tLAD
Logic array delay
3.1
5.0
6.0
ns
tLAC
Logic control array delay
3.1
5.0
6.0
ns
tIOE
Internal output enable delay
0.9
2.0
3.0
ns
tOD1
Output buffer and pad delay
C1 = 35 pF
0.5
1.5
4.0
ns
tOD2
Output buffer and pad delay
C1 = 35 pF (6)
1.0
2.0
5.0
ns
tOD3
Output buffer and pad delay
C1 = 35 pF
5.5
5.5
7.0
ns
tZX1
Output buffer enable delay
C1 = 35 pF
4.0
5.0
6.0
ns
tZX2
Output buffer enable delay
C1 = 35 pF (6)
4.5
5.5
7.0
ns
tZX3
Output buffer enable delay
C1 = 35 pF
9.0
9.0
10.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
4.0
5.0
6.0
ns
tSU
Register setup time
1.1
2.0
4.0
ns
Table 35. EPM7192S External Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
-15
Min
Max
Min
Max
Min
Max


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66 


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn