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74VHC123ASJX 数据表(PDF) 8 Page - Fairchild Semiconductor |
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74VHC123ASJX 数据表(HTML) 8 Page - Fairchild Semiconductor |
8 / 14 page ©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC123A Rev. 1.2 8 AC Electrical Characteristics(4) Notes: 4. Refer to Timing Chart. 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD • VCC • fIN+ ICC 1 • Duty / 100 + I CC / 2 (per Circuit) ICC 1: Active Supply Current Duty: % Symbol Parameter VCC (V) Conditions TA = 25°C TA = –40°C to +85°C Units Min. Typ. Max. Min. Max. tPLH, tPHL Propagation Delay Time (A, B–Q, Q) 3.3 ± 0.3 CL = 15 pF 13.4 20.6 1.0 24.0 ns CL = 50 pF 15.9 24.1 1.0 27.5 5.0 ± 0.5 CL = 15 pF 8.1 12.0 1.0 14.0 ns CL = 50 pF 9.6 14.0 1.0 16.0 tPLH, tPHL Propagation Delay Time (CLR Trigger—Q, Q) 3.3 ± 0.3 CL = 15 pF 14.5 22.4 1.0 26.0 ns CL = 50 pF 17.0 25.9 1.0 29.5 5.0 ± 0.5 CL = 15 pF 8.7 12.9 1.0 15.0 ns CL = 50 pF 10.2 14.9 1.0 17.0 tPLH, tPHL Propagation Delay Time (CLR—Q, Q) 3.3 ± 0.3 CL = 15 pF 10.3 15.8 1.0 18.5 ns CL = 50 pF 12.8 19.3 1.0 22.0 5.0 ± 0.5 CL = 15 pF 6.3 9.4 1.0 11.0 ns CL = 50 pF 7.8 11.4 1.0 13.0 tWOUT Output Pulse Width 3.3 ± 0.3 CL = 50pF, Cx = 28pF, Rx = 2kΩ 160 240 300 ns 5.0 ± 0.5 133 200 240 3.3 ± 0.3 CL = 50pF, Cx = 0.01µF, Rx = 10kΩ 90 100 110 90 110 µs 5.0 ± 0.5 90 100 110 90 110 3.3 ± 0.3 CL = 50pF, Cx = 0.1µF, Rx = 1kΩ 0.9 1.0 1.1 0.9 1.1 ms 5.0 ± 0.5 0.9 1.0 1.1 0.9 1.1 ∆t WOUT Output Pulse Width Error Between Circuits (In same Package) ±1 % CIN Input Capacitance VCC = Open 4 10 10 pF CPD Power Dissipation Capacitance (5) 73 pF |
类似零件编号 - 74VHC123ASJX |
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类似说明 - 74VHC123ASJX |
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