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SC16C554BIB64 数据表(PDF) 10 Page - NXP Semiconductors

部件名 SC16C554BIB64
功能描述  5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

SC16C554BIB64 数据表(HTML) 10 Page - NXP Semiconductors

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SC16C554B_554DB
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 8 June 2010
10 of 58
NXP Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type
Description
PLCC68
LQFP64
LQFP80 HVQFN48
16/68
31
-
-
14
I
16/68 Interface type select (input with internal
pull-up). This input provides the 16 (Intel) or 68
(Motorola) bus interface type select. The functions of
IOR, IOW, INTA to INTD, and CSA to CSD are
re-assigned with the logic state of this pin. When this
pin is a logic 1, the 16 mode interface (16C554) is
selected. When this pin is a logic 0, the 68 mode
interface (68C554) is selected. When this pin is a
logic 0, IOW is re-assigned to R/W, RESET is
re-assigned to RESET, IOR is not used, and
INTA to INTD are connected in a wire-OR configuration.
The wire-OR outputs are connected internally to the
open-drain IRQ signal output. This pin is not available
on 64-pin packages which operate in the 16 mode only.
A0
34
24
48
17
I
Address 0 select bit. Internal registers address
selection in 16 and 68 modes.
A1
33
23
47
16
I
Address 1 select bit. Internal registers address
selection in 16 and 68 modes.
A2
32
22
46
15
I
Address 2 select bit. Internal registers address
selection in 16 and 68 modes.
A3
20
-
-
9
I
Address 3 to Address 4 select bits. When the 68
mode is selected, these pins are used to address or
select individual UARTs (providing CS is a logic 0). In
the 16 mode, these pins are re-assigned as chip
selects, see CSB and CSC.
A4
50
-
-
31
I
CDA
964
19
-
I
Carrier Detect (active LOW). These inputs are
associated with individual UART channels A through D.
A logic 0 on this pin indicates that a carrier has been
detected by the modem for that channel.
CDB
27
18
42
-
I
CDC
43
31
59
24
I
CDD
61
49
2
-
I
CS
16
-
-
5
I
Chip Select (active LOW). In the 68 mode, this pin
functions as a multiple channel chip enable. In this
case, all four UARTs (A to D) are enabled when the CS
pin is a logic 0. An individual UART channel is selected
by the data contents of address bits A3 to A4. when the
16 mode is selected (68-pin devices), this pin functions
as CSA (see definition under CSA, CSB).
CSA
16
7
28
5
I
Chip Select A, B, C, D (active LOW). This function is
associated with the 16 mode only, and for individual
channels ‘A’ through ‘D’. When in 16 mode, these pins
enable data transfers between the user CPU and the
SC16C554B/554DB for the channel(s) addressed.
Individual UART sections (A, B, C, D) are addressed by
providing a logic 0 on the respective CSA to CSD pin.
When the 68 mode is selected, the functions of these
pins are re-assigned. 68 mode functions are described
under their respective name/pin headings.
CSB
20
11
33
9
I
CSC
50
38
68
31
I
CSD
54
42
73
35
I


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