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SC16C554BIB64 数据表(PDF) 34 Page - NXP Semiconductors |
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SC16C554BIB64 数据表(HTML) 34 Page - NXP Semiconductors |
34 / 58 page SC16C554B_554DB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 June 2010 34 of 58 NXP Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19. Modem Control Register bits description Bit Symbol Description 7:6 MCR[7:6] Reserved; set to ‘0’. 5 MCR[5] Autoflow control enable. 4 MCR[4] Loopback. Enable the local Loopback mode (diagnostics). In this mode the transmitter output (TXn) and the receiver input (RXn), CTS, DSR, CD, and RI are disconnected from the SC16C554B/554DB I/O pins. Internally the modem data and control pins are connected into a loopback data configuration (see Figure 14). In this mode, the receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ sources are switched to the lower four bits of the Modem Control. Interrupts continue to be controlled by the IER register. logic 0 = disable Loopback mode (normal default condition) logic 1 = enable local Loopback mode (diagnostics) 3MCR[3] OP2, INTn enable. Used to control the modem CD signal in the Loopback mode. logic 0 = forces INTA to INTD outputs to the 3-state mode during the 16 mode (normal default condition). In the Loopback mode, sets OP2 (CD) internally to a logic 1. logic 1 = forces the INTA to INTD outputs to the active mode during the 16 mode. In the Loopback mode, sets OP2 (CD) internally to a logic 0. 2MCR[2] OP1. This bit is used in the Loopback mode only. In the Loopback mode, this bit is used to write the state of the modem RI interface signal via OP1. 1MCR[1] RTS logic 0 = force RTS output to a logic 1 (normal default condition) logic 1 = force RTS output to a logic 0 Automatic RTS may be used for hardware flow control by enabling MCR[5]. 0MCR[0] DTR logic 0 = force DTR output to a logic 1 (normal default condition) logic 1 = force DTR output to a logic 0 |
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