SC16C554BIB64 datasheet(18/58 Pages) NXP

部件名	SC16C554BIB64

功能描述	5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

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制造商	NXP [NXP Semiconductors]

网页	http://www.nxp.com

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18 / 58 page

SC16C554B_554DB

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Product data sheet

Rev. 4 — 8 June 2010

18 of 58

NXP Semiconductors

SC16C554B/554DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

6.4 Autoflow control (see Figure 9)

Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input

must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes

active when the receiver needs more data and notifies the sending serial device. When

RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has

space for the data; thus, overrun errors are eliminated using UART 1 and UART 2 from a

SC16C554B/554DB with the autoflow control enabled. If not, overrun errors occur when

the transmit data rate exceeds the receiver FIFO read latency.

6.4.1 Auto-RTS (see Figure 9)

Auto-RTS data flow control originates in the receiver timing and control block (see block

diagrams in Figure 1 and Figure 2) and is linked to the programmed receiver FIFO trigger

level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 11),

RTS is de-asserted. With trigger levels of 1, 4, and 8, the sending UART may send an

additional byte after the trigger level is reached (assuming the sending UART has another

byte to send) because it may not recognize the de-assertion of RTS until after it has

begun sending the additional byte. RTS is automatically reasserted once the RX FIFO is

emptied by reading the receiver buffer register. When the trigger level is 14 (see

Figure 12), RTS is de-asserted after the first data bit of the 16th character is present on

the RX line. RTS is reasserted when the RX FIFO has at least one available byte space.

Remark: Auto-RTS is not supported in channel D of the HVQFN48 package, therefore

MCR[5] of channel D should not be written.

6.4.2 Auto-CTS (see Figure 9)

The transmitter circuitry checks CTS before sending the next data byte. When CTS is

active, it sends the next byte. To stop the transmitter from sending the following byte, CTS

must be released before the middle of the last stop bit that is currently being sent (see

Figure 10). The auto-CTS function reduces interrupts to the host system. When flow

control is enabled, CTS level changes do not trigger host interrupts because the device

automatically controls its own transmitter. Without auto-CTS, the transmitter sends any

data present in the transmit FIFO and a receiver overrun error may result.

Fig 9.

Autoflow control (auto-RTS and auto-CTS) example

RX

FIFO

FLOW

CONTROL

TX

FIFO

PARALLEL

TO SERIAL

TX

FIFO

RX

FIFO

UART 1

UART 2

D7 to D0

RX

TX

RTS

CTS

TX

RX

CTS

RTS

D7 to D0

002aaa228

SERIAL TO

PARALLEL

SERIAL TO

PARALLEL

FLOW

CONTROL

FLOW

CONTROL

FLOW

CONTROL

PARALLEL

TO SERIAL

类似零件编号 - SC16C554BIB64

制造商	部件名	数据表	功能描述
NXP Semiconductors	SC16C554BIB64	253Kb / 51P	5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Rev. 01-9 February 2005
NXP Semiconductors	SC16C554BIB64	1Mb / 58P	5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Rev. 4-8 June 2010

More results

类似说明 - SC16C554BIB64

制造商	部件名	数据表	功能描述
NXP Semiconductors	SC16C554B	253Kb / 51P	5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Rev. 01-9 February 2005
	SC16C554B	1Mb / 58P	5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Rev. 4-8 June 2010
	SC16C754B	259Kb / 50P	5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Rev. 02-13 June 2005
	SC16C754B	252Kb / 51P	5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Rev. 04-6 October 2008
	SC16C2550B	211Kb / 43P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 04-15 February 2007
	SC16C2552B	188Kb / 38P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 03-12 February 2009
	SC16C2550B	221Kb / 43P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 05-12 January 2009
	SC16C2550B	200Kb / 42P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 02-14 December 2004
	SC16C752B	225Kb / 47P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Rev. 03-14 December 2004
	SC16C752B	226Kb / 47P	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Rev. 05-2 October 2008

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SC16C554BIB64 数据表(PDF) 18 Page - NXP Semiconductors

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类似说明 - SC16C554BIB64

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