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AM3892CCYG135 数据表(PDF) 10 Page - Texas Instruments |
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AM3892CCYG135 数据表(HTML) 10 Page - Texas Instruments |
10 / 308 page AM3894 AM3892 SPRS681E – OCTOBER 2010 – REVISED JULY 2012 www.ti.com 2.3.1 ARM Cortex-A8 RISC Processor The ARM Cortex-A8 subsystem integrates the ARM Cortex-A8 processor. The ARM Cortex-A8 processor is a member of ARM Cortex family of general-purpose processors. This processor is targeted at multi- tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM Cortex-A8 processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM Cortex-A8 processor has a Harvard architecture and provides a complete high-performance subsystem, including: • ARM Cortex-A8 integer core • Superscalar ARMv7 instruction set • Thumb-2 instruction set • Jazelle RCT acceleration • CP14 debug coprocessor • CP15 system control coprocessor • NEON 64-/128-bit hybrid SIMD engine for multimedia • Enhanced memory management unit (MMU) • Separate level-1 instruction and data caches • Integrated level-2 cache • 128-bit interconnect to system memories and peripherals • Embedded trace module (ETM). 2.3.2 Embedded Trace Module (ETM) To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an embedded trace module (ETM). The ETM consists of two parts: • The Trace port provides real-time trace capability for the ARM Cortex-A8. • Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers. The ARM Cortex-A8 trace port is connected to the system-level embedded trace buffer (ETB). The ETB has a 32KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data. For more details on the ETB, see Section 8.4.2. 2.3.3 ARM Cortex-A8 Interrupt Controller (AINTC) The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor. For more details on the AINTC, see Section 7.4. 2.3.4 System Interconnect The ARM Cortex-A8 processor in connected through the arbiter to both an L3 interconnect port and a DMM port. The DMM port is 128-bits wide and provides the ARM Cortex-A8 direct access to the DDR memories, while the L3 interconnect port is 64-bits wide and provides access to the remaining device modules. 10 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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