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AD9961 数据表(PDF) 7 Page - Analog Devices |
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AD9961 数据表(HTML) 7 Page - Analog Devices |
7 / 61 page Data Sheet AD9961/AD9963 Rev. A | Page 7 of 60 Table 5. Digital Logic Level Specifications Parameter Conditions Min Typ Max Unit CMOS INPUT LOGIC LEVEL V IN Logic High DRVDD = 1.8 V 1.2 V V IN Logic High DRVDD = 2.5 V 1.7 V V IN Logic High DRVDD = 3.3 V 2.0 V V IN Logic Low DRVDD = 1.8 V 0.5 V V IN Logic Low DRVDD = 2.5 V 0.7 V V IN Logic Low DRVDD = 3.3 V 0.8 V CMOS OUTPUT LOGIC LEVEL V OUT Logic High DRVDD = 1.8 V 1.35 V V OUT Logic High DRVDD = 2.5 V 2.05 V V OUT Logic High DRVDD = 3.3 V 2.4 V V OUT Logic Low DRVDD = 1.8 V 0.4 V V OUT Logic Low DRVDD = 2.5 V 0.4 V V OUT Logic Low DRVDD = 3.3 V 0.4 V DAC CLOCK INPUT Differential Peak-to-Peak Voltage 200 400 CLK33V mV p-p diff Duty Cycle 45 55 % Slew Rate 0.1 V/ns DIRECT CLOCKING Clock Rate CLKP/CLKN inputs 0.1 200 MHz DLL ENABLED % Clock Rate DLL delay line output 100 310 MHz SERIAL PERIPHERAL INTERFACE Maximum Clock Rate 50 MHz Minimum Pulse Width High (t HIGH) 10 ns Minimum Pulse Width Low (t LOW) 10 ns Setup Time, SDIO (Data In) to SCLK (t DS) 5.0 ns Hold Time, SDI to SCLK (t DH) 5.0 ns Data Valid, SDIO (Data Out) to SCLK (t DV) 5.0 ns Setup Time, CS to SCLK (tS) 5.0 ns |
类似零件编号 - AD9961 |
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类似说明 - AD9961 |
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