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TSB41AB1GQE 数据表(PDF) 3 Page - Texas Instruments |
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TSB41AB1GQE 数据表(HTML) 3 Page - Texas Instruments |
3 / 70 page TSB41AB1 IEEE 1394a2000 ONEPORT CABLE TRANSCEIVER/ARBITER SLLS423I − JUNE 2000 − REVISED MARCH 2005 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 description (continued) connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with recommended values of 5 k Ω and 220 pF. The values of the external line termination resistors are designed to meet IEEE Std 1394-1995 when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current-setting resistor has a value of 6.34 k Ω ±1.0%. When the power supply of the TSB41AB1 is off while the twisted-pair cables are connected, the TSB41AB1 transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the device power plane. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDD through a 1-kΩ resistor, SE should be tied to ground through a 1-k Ω resistor, and SM should be connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are tied high through a 1-k Ω resistor or hardwired low as a function of the equipment design. The PC0 – PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager (IRM) or for bus manager (BM). The TSB41AB1 supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend mechanism allows pairs of directly connected ports to be placed into a low-power state (suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBIAS. When the port of the TSB41AB1 is suspended, all circuits except the band gap reference generator and bias detection circuit is powered down, resulting in significant power savings. For additional details of suspend/resume operation see IEEE 1394a-2000. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBIAS output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The cable-not-active (CNA) output terminal (64-terminal PAP package only) is asserted high when there are no twisted-pair cable ports receiving incoming bias (that is, they are either disconnected or suspended), and can be used along with LPS to determine when to power down the TSB41AB1. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET terminal so as to force a reset of the TSB41AB1 internal logic. The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the Application Information section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit). The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise. When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41AB1 continues the necessary repeater functions |
类似零件编号 - TSB41AB1GQE |
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类似说明 - TSB41AB1GQE |
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