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MCP47X6A7-E 数据表(PDF) 11 Page - Microchip Technology |
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MCP47X6A7-E 数据表(HTML) 11 Page - Microchip Technology |
11 / 86 page © 2011-2012 Microchip Technology Inc. DS22272C-page 11 MCP4706/4716/4726 106 THD:DAT Data input hold time 100 kHz mode 0 — ns 2.7V-5.5V, Note 6 400 kHz mode 0 — ns 2.7V-5.5V, Note 6 1.7 MHz mode 0 — ns 4.5V-5.5V, Note 6 3.4 MHz mode 0 — ns 4.5V-5.5V, Note 6 107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 1.7 MHz mode 10 — ns 3.4 MHz mode 10 — ns 109 TAA Output valid from clock 100 kHz mode — 3750 ns Note 1, Note 8 400 kHz mode — 1200 ns 1.7 MHz mode — 150 ns Cb = 100 pF, Note 1, Note 7, Note 8 — 310 ns Cb = 400 pF, Note 1, Note 5, Note 8 3.4 MHz mode — 150 ns Cb = 100 pF, Note 1, Note 8 110 TBUF Bus free time 100 kHz mode 4700 — ns Time the bus must be free before a new transmission can start 400 kHz mode 1300 — ns 1.7 MHz mode N/A — ns 3.4 MHz mode N/A — ns TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C™ AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature -40 °C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in Electrical Characteristics Param. No. Sym Characteristic Min Max Units Conditions Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I 2C bus specification) before the SCL line is released. 3: The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use Cb in pF for the calculations. 5: Not Tested. This parameter ensured by characterization. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. 7: Ensured by the TAA 3.4 MHz specification test. 8: The specification is not part of the I 2 C specification. TAA = THD:DAT + TFSDA (or TRSDA). |
类似零件编号 - MCP47X6A7-E |
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类似说明 - MCP47X6A7-E |
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