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ADP7105ARDZ1.8 Datasheet(数据表) 18 Page  Analog Devices 

18 page ADP7105 Data Sheet Rev. 0  Page 18 of 28 APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor The ADP7105 is designed for operation with small, spacesaving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 1 µF capacitance with an ESR of 1 Ω or less is recommended to ensure the stability of the ADP7105. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP7105 to large changes in load current. Figure 63 shows the transient responses for an output capacitance value of 1 µF. Figure 63. Output Transient Response, VOUT = 1.8 V, COUT = 1 µF Input Bypass Capacitor Connecting a 1 µF capacitor from VIN to GND reduces the circuit sensitivity to PCB layout, especially when long input traces or high source impedance is encountered. If greater than 1 µF of output capacitance is required, increase the input capacitor to match it. Input and Output Capacitor Properties Any good quality ceramic capacitors can be used with the ADP7105, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufac tured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V to 25 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. Figure 64 shows the capacitance vs. voltage bias characteristic of an 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is ~±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating. Figure 64. Capacitance vs. Voltage Bias Characteristic Use Equation 1 to determine the worstcase capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worstcase capacitor temperature coefficient. TOL is the worstcase component tolerance. In this example, the worstcase temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.94 μF at 1.8 V, as shown in Figure 64. Substituting these values in Equation 1 yields CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO regulator overtemperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP7105, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. CH2 50mV CH1 500mA M 20µs A CH1 270mA 1 2 T 10% Ω LOAD CURRENT OUTPUT VOLTAGE 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 VOLTAGE (V) 
