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RC5061 数据表(PDF) 15 Page - Fairchild Semiconductor |
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RC5061 数据表(HTML) 15 Page - Fairchild Semiconductor |
15 / 18 page PRODUCT SPECIFICATION RC5061 REV. 1.0.0 7/6/00 15 Adjusting the Linear Regulators’ Output Voltages Any or all of the linear regulators’ outputs may be adjusted high to compensate for voltage drop along traces, as shown in Figure 6. Figure 6. Adjusting the Output Voltage of the Linear Regulator The resistor value should be chosen as For example, to get the VTT voltage to be 1.55V instead of 1.50V, use R = 10K Ω * [(1.55/1.50) – 1] = 333Ω. PCB Layout Guidelines • Placement of the MOSFETs relative to the RC5061 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the RC5061 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difficult to suppress. • In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5061. That is, traces that connect to pins 1, 2, 19, and 20 (HIDRV, SW, LODRV and VCCP) should be kept far away from the traces that connect to pins 3, 16 and 17. • Place the 0.1µF decoupling capacitors as close to the RC5061 pins as possible. Extra lead length on these reduces their ability to suppress noise. • Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins. • Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the first bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1µF decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter. • Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converter’s performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5. • A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11. Additional Information For additional information contact Fairchild Semiconductor at http://www.fairchildsemi.com/cf/tsg.htm or contact an autho- rized representative in your area. VFB VGATE VOUT 10K Ω R R 10K Ω* –1 Vout Vnom = |
类似零件编号 - RC5061 |
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类似说明 - RC5061 |
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