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RC5061 数据表(PDF) 13 Page - Fairchild Semiconductor

部件名 RC5061
功能描述  High Performance Programmable Synchronous DC-DC Controller for Multi-Voltage Platforms
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制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
标志 FAIRCHILD - Fairchild Semiconductor

RC5061 数据表(HTML) 13 Page - Fairchild Semiconductor

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PRODUCT SPECIFICATION
RC5061
REV. 1.0.0 7/6/00
13
Design Considerations and Component
Selection
Additional information on design and component selection
may be found in Fairchild’s Application Note 57.
MOSFET Selection
This application requires N-channel Logic Level Enhancement
Mode Field Effect Transistors. Desired characteristics are as
follows:
• Low Static Drain-Source On-Resistance, RDS,ON < 20mΩ
(lower is better)
• Low gate drive voltage, VGS = 4.5V rated
• Power package with low Thermal Resistance
• Drain-Source voltage rating > 15V.
The on-resistance (RDS,ON) is the primary parameter for
MOSFET selection. The on-resistance determines the power
dissipation within the MOSFET and therefore significantly
affects the efficiency of the DC-DC Converter. For details
and a spreadsheet on MOSFET selection, refer to Applica-
tions Bulletin AB-8.
Inductor Selection
Choosing the value of the inductor is a tradeoff between
allowable ripple voltage and required transient response. The
system designer can choose any value within the allowed
minimum to maximum range in order to either minimize ripple
or maximize transient performance. The first order equation
(close approximation) for minimum inductance is:
where:
Vin = Input Power Supply
Vout = Output Voltage
f = DC/DC converter switching frequency
ESR = Equivalent series resistance of all output capacitors in
parallel
Vripple = Maximum peak to peak output ripple voltage budget.
The first order equation for maximum allowed inductance is:
where:
Co = The total output capacitance
Ipp = Maximum to minimum load transient current
Vtb = The output voltage tolerance budget allocated to load
transient
Dm = Maximum duty cycle for the DC/DC converter (usually
95%).
Some margin should be maintained away from both Lmin and
Lmax. Adding margin by increasing L almost always adds
expense since all the variables are predetermined by system
performance except for CO, which must be increased to
increase L. Adding margin by decreasing L can be done by
purchasing capacitors with lower ESR. The RC5061 pro-
vides significant cost savings for the newer CPU systems
that typically run at high supply current.
RC5061 Short Circuit Current Characteristics
The RC5061 protects against output short circuit on the core
supply by turning off both the high-side and low-side
MOSFETs and resetting softstart. The short circuit limit is
set with the RS resistor, as given by the formula
with IDetect ≈ 50µA, ISC is the desired current limit, and
RDS,on the high-side MOSFET’s on resistance. Remember to
make the RS large enough to include the effects of initial tol-
erance and temperature variation on the MOSFET’s RDS,on.
Alternately, use of a sense resistor in series with the source
of the MOSFET eliminates this source of inaccuracy in the
current limit. The value of RS should be less than 8.3KΩ. If a
greater value is necessary, a lower RDS,on MOSFET should
be used instead.
As an example, Figure 4 shows the typical characteristic of
the DC-DC converter circuit with an FDB6030L high-side
MOSFET (RDS = 20mΩ maximum at 25°C * 1.25 at 75°C =
25m
Ω) and a 8.2KΩ R
S.
Figure 4. RC5061 Short Circuit Characteristic
The converter exhibits a normal load regulation characteristic
until the voltage across the MOSFET exceeds the internal
short circuit threshold of 50µA * 8.2K
Ω = 410mV, which
occurs at 410mV/25m
Ω = 16.4A. (Note that this current limit
level can be as high as 410mV/15m
Ω = 27A, if the MOSFET
has typical RDS,on rather than maximum, and is at 25°C).
At this point, the internal comparator trips and signals the con-
troller to discharge the softstart capacitor. This causes a drastic
reduction in the output voltage as the load regulation collapses
into the short circuit control mode. With a 40m
Ω output short,
Lmin
(Vin – Vout)
f
x
Vout
Vin
x
ESR
Vripple
=
Lmax
(Vin – Vout) Dm Vtb
Ipp2
= 2CO
RS
ISC *RDS, on
IDetect
=
0
5
10
15
20
25
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
CPU Output Voltage vs. Output Current


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