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RC5061 数据表(PDF) 12 Page - Fairchild Semiconductor |
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RC5061 数据表(HTML) 12 Page - Fairchild Semiconductor |
12 / 18 page RC5061 PRODUCT SPECIFICATION 12 REV. 1.0.0 7/6/00 Test Parameters Figure 3. Ouput Drive Timing Diagram Application Information The RC5061 Controller The RC5061 is a programmable synchronous DC-DC con- troller IC. When designed around the appropriate external components, the RC5061 can be configured to deliver more than 16A of output current, as appropriate for the Katmai and Coppermine and other processors. The RC5061 functions as a fixed frequency PWM step down regulator. Main Control Loop Refer to the RC5061 Block Diagram on page 1. The RC5061 implements “summing mode control”, which is different from both classical voltage-mode and current-mode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a comparator which provides the input to the digital control block. The signal conditioning section accepts input from the DROOP (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The first, the voltage control path, amplifies the difference between the VFB signal and the reference voltage from the DAC and presents the output to one of the summing amplifier inputs. The second, current control path, takes the difference between the DROOP and SW pins when the high-side MOSFET is on, reproducing the voltage across the MOSFET and thus the input current; it presents the resulting signal to another input of the summing amplifier. These two signals are then summed together. This output is then presented to a comparator looking at the oscillator ramp, which provides the main PWM control signal to the digital control block. The digital control block takes the analog comparator input and the main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These two outputs control the external power MOSFETs. There is an additional comparator in the analog control section whose function is to set the point at which the RC5061 current limit comparator disables the output drive signals to the external power MOSFETs. High Current Output Drivers The RC5061 contains two identical high current output drivers that utilize high speed bipolar transistors in a push-pull config- uration. The drivers’ power and ground are separated from the chip’s power and ground for switching noise immunity. The power supply pin, VCCP, is supplied from an external 12V source through a series 33 Ω resistor. The resulting volt- age is sufficient to provide the gate to source drive to the external MOSFETs required in order to achieve a low RDS,ON. Internal Voltage Reference The reference included in the RC5061 is a precision band-gap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. The DAC monitors the 5 voltage identification pins, VID0-4. When the VID4 pin is at logic HIGH, the DAC scales the reference voltage from 2.0V to 3.5V in 100mV increments. When VID4 is pulled LOW, the DAC scales the reference from 1.30V to 2.05V in 50mV increments. All VID codes are available, includ- ing those below 1.80V. Power Good (PWRGD) The RC5061 Power Good function is designed in accordance with the Pentium III DC-DC converter specifications and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage deviate more than ±12% of its nominal setpoint. The Power Good flag provides no other control function to the RC5061. Output Enable/Soft Start (ENABLE/SS) The RC5061 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. Even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nF) to softstart the switching. A larger value may occasionally be required if the converter has a very large capacitor at its output. Over-Voltage Protection The RC5061 constantly monitors the output voltage for protec- tion against over-voltage conditions. If the voltage at the VFB pin exceeds the selected program voltage, an over-voltage condition is assumed and the RC5061 disables the output drive signal to the external high-side MOSFET. The DC-DC converter returns to normal operation after the output voltage returns to normal levels. Oscillator The RC5061 oscillator section uses a fixed frequency of operation of 300KHz. tR 5V tDT tDT tF HIDRV to SW LODRV 2V 2V 2V 5V 2V |
类似零件编号 - RC5061 |
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类似说明 - RC5061 |
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