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EPM7032 数据表(PDF) 8 Page - Altera Corporation |
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EPM7032 数据表(HTML) 8 Page - Altera Corporation |
8 / 66 page 8 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices. Figure 2. MAX 7000E & MAX 7000S Device Block Diagram Logic Array Blocks The MAX 7000 device architecture is based on the linking of high- performance, flexible, logic array modules called logic array blocks (LABs). LABs consist of 16-macrocell arrays, as shown in Figures 1 and 2. Multiple LABs are linked together via the programmable interconnect array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and macrocells. 6 6 INPUT/GCLRn 6 Output Enables 6 Output Enables 16 36 36 16 I/O Control Block LAB C LAB D I/O Control Block 6 16 36 36 16 I/O Control Block LAB A LAB B I/O Control Block 6 6 to16 INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 6 to 16 I/O Pins 6 to 16 I/O Pins 6 to 16 I/O Pins 6 to 16 I/O Pins 6 to16 6 to16 6 to16 6 to16 6 to16 6 to16 6 to16 6 to16 6 to16 6 to16 6 to16 Macrocells 1 to 16 Macrocells 17 to 32 Macrocells 33 to 48 Macrocells 49 to 64 PIA |
类似零件编号 - EPM7032 |
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类似说明 - EPM7032 |
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