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EPM7032 数据表(PDF) 49 Page - Altera Corporation |
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EPM7032 数据表(HTML) 49 Page - Altera Corporation |
49 / 66 page Altera Corporation 49 MAX 7000 Programmable Logic Device Family Data Sheet tAH Array clock hold time 1.8 3.0 4.0 ns tACO1 Array clock to output delay C1 = 35 pF 7.8 10.0 15.0 ns tACH Array clock high time 3.0 4.0 6.0 ns tACL Array clock low time 3.0 4.0 6.0 ns tCPPW Minimum pulse width for clear and preset (2) 3.0 4.0 6.0 ns tODH Output data hold time after clock C1 = 35 pF (3) 1.0 1.0 1.0 ns tCNT Minimum global clock period 8.0 10.0 13.0 ns fCNT Maximum internal global clock frequency (4) 125.0 100.0 76.9 MHz tACNT Minimum array clock period 8.0 10.0 13.0 ns fACNT Maximum internal array clock frequency (4) 125.0 100.0 76.9 MHz fMAX Maximum clock frequency (5) 166.7 125.0 100.0 MHz Table 36. EPM7192S Internal Timing Parameters (Part 1 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -7 -10 -15 Min Max Min Max Min Max tIN Input pad and buffer delay 0.3 0.5 2.0 ns tIO I/O input pad and buffer delay 0.3 0.5 2.0 ns tFIN Fast input delay 3.2 1.0 2.0 ns tSEXP Shared expander delay 4.2 5.0 8.0 ns tPEXP Parallel expander delay 1.2 0.8 1.0 ns tLAD Logic array delay 3.1 5.0 6.0 ns tLAC Logic control array delay 3.1 5.0 6.0 ns tIOE Internal output enable delay 0.9 2.0 3.0 ns tOD1 Output buffer and pad delay C1 = 35 pF 0.5 1.5 4.0 ns tOD2 Output buffer and pad delay C1 = 35 pF (6) 1.0 2.0 5.0 ns tOD3 Output buffer and pad delay C1 = 35 pF 5.5 5.5 7.0 ns tZX1 Output buffer enable delay C1 = 35 pF 4.0 5.0 6.0 ns tZX2 Output buffer enable delay C1 = 35 pF (6) 4.5 5.5 7.0 ns tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 10.0 ns tXZ Output buffer disable delay C1 = 5 pF 4.0 5.0 6.0 ns tSU Register setup time 1.1 2.0 4.0 ns Table 35. EPM7192S External Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -7 -10 -15 Min Max Min Max Min Max |
类似零件编号 - EPM7032 |
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类似说明 - EPM7032 |
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