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EP2AGX260EF29C5N 数据表(PDF) 22 Page - Altera Corporation |
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EP2AGX260EF29C5N 数据表(HTML) 22 Page - Altera Corporation |
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22 / 78 page  Spread-spectrum downspread PCIe — 0 to –0.5% —— 0 to –0.5% —— 0 to –0.5% —— 0 to –0.5% —— On-chip termination resistors — — 100 — — 100 — — 100 — — 100 — VICM (AC coupled) — 1100 ± 5% 1100 ± 5% 1100 ± 5% 1100 ± 5% mV VICM (DC coupled) HCSL I/O standard for PCIe reference clock 250 — 550 250 — 550 250 — 550 250 — 550 mV Transmitter REFCLK Phase Noise 10 Hz — — -50 — — -50 — — -50 — — -50 dBc/Hz 100 Hz — — -80 — — -80 — — -80 — — -80 dBc/Hz 1 KHz — — -110 — — -110 — — -110 — — -110 dBc/Hz 10 KHz — — -120 — — -120 — — -120 — — -120 dBc/Hz 100 KHz — — -120 — — -120 — — -120 — — -120 dBc/Hz 1 MHz — — -130 — — -130 — — -130 — — -130 dBc/Hz Transmitter REFCLK Phase Jitter (rms) for 100 MHz REFCLK (3) 10 KHz to 20 MHz —— 3 — — 3 — — 3 — — 3 ps Rref —— 2000 ±1% —— 2000 ±1% —— 2000 ±1% —— 2000 ± 1% — Transceiver Clocks Calibration block clock frequency (cal_blk_clk) — 10 — 125 10 — 125 10 — 125 10 — 125 MHz Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 2 of 7) Symbol/ Description Condition I3 C4 C5 and I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max |
类似零件编号 - EP2AGX260EF29C5N |
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类似说明 - EP2AGX260EF29C5N |
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