AD7564BRZ datasheet(5/17 Pages) AD

部件名	AD7564BRZ

功能描述	LC2MOS 3.3 V/5 V, Low Power, Quad 12-Bit DAC

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制造商	AD [Analog Devices]

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–5–

REV.

3

AD7564

Timing Specifications1 (T

A = TMIN to TMAX unless otherwise noted)

Limit at

Parameter

VDD = +3 V to +3.6 V VDD = +4.75 V to +5.25 V

Units

Description

t1

180

100

ns min

CLKIN Cycle Time

t2

80

40

ns min

CLKIN High Time

t3

80

40

ns min

CLKIN Low Time

t4

50

30

ns min

FSIN

Setup Time

t5

50

30

ns min

Data Setup Time

t6

10

5

ns min

Data Hold Time

t7

125

90

ns min

FSIN

Hold Time

t8

2

100

70

ns max

SDOUT Valid After CLKIN Falling Edge

t9

80

40

ns min

LDAC

, CLR Pulse Width

NOTES

1Not production tested. Guaranteed by characterization at initial product release. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

DD) and timed

from a voltage level of 1.6 V for a VDD of 5 V and from a voltage level 1.35 V for a VDD of 3.3 V.

2t

8 is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with a VDD of 5 V and 0.6 V or 2.1 V for a VDD

of 3.3 V.

DB15

DB0

t

2

t

3

t

4

t

5

t

7

t

8

t

9

DB0

t

6

t1

FSIN(I)

CLKIN(I)

SDIN(I)

SDOUT(O)

LDAC, CLR

Figure 1. Timing Diagram

1.6mA

+1.6V

200µA

CL

50pF

TO OUTPUT

IOL

IOH

Figure 2. Load Circuit for Digital Output Timing Specifications

B

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AD7564BRZ 数据表(PDF) 5 Page - Analog Devices

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AD7564BRZ 数据表(PDF) 5 Page - Analog Devices

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