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AD7226KR-REEL 数据表(PDF) 6 Page - Analog Devices |
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AD7226KR-REEL 数据表(HTML) 6 Page - Analog Devices |
6 / 16 page REV. –6– AD7226 INTERFACE LOGIC INFORMATION Address lines A0 and A1 select which DAC will accept data from the input port. Table I shows the selection table for the four DACs with Figure 4 showing the input control logic. When the WR signal is LOW, the input latches of the selected DAC are transparent and its output responds to activity on the data bus. The data is latched into the addressed DAC latch on the rising edge of WR. While WR is high the analog outputs remain at the value corresponding to the data held in their respective latches. Table I. AD7226 Truth Table AD7226 Control Inputs AD7226 WR A1 A0 Operation HX XNo Operation Device Not Selected LL L DAC A Transparent LL DAC A Latched LL H DAC B Transparent LH DAC B Latched LH L DAC C Transparent HL DAC C Latched LH H DAC D Transparent HH DAC D Latched L = Low State, H = High State, X = Don’t Care A0 A1 WR TO LATCH A TO LATCH B TO LATCH C TO LATCH D Figure 4. Input Control Logic t DS t DH t AH t AS VINL VINH VINH VINL VDD VDD VDD DATA ADDRESS WR 0 0 0 t WR NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF VDD. t r = tf = 20ns OVER VDD RANGE. 2. TIMING MEASUREMENT REFERENCE LEVEL IS 3. SELECTED INPUT LATCH IS TRANSPARENT WHILE WR IS LOW, THUS INVALID DATA DURING THIS TIME CAN CAUSE SPURIOUS OUTPUTS. VINH + VINL 2 Figure 5. Write Cycle Timing Diagram D |
类似零件编号 - AD7226KR-REEL |
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类似说明 - AD7226KR-REEL |
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