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AD6620ASZ 数据表(PDF) 7 Page - Analog Devices

部件名 AD6620ASZ
功能描述  67 MSPS Digital Receive Signal Processor
Download  44 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD6620ASZ 数据表(HTML) 7 Page - Analog Devices

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AD6620
–7–
REV. A
TIMING DIAGRAMS
CLK, INPUTS, PARALLEL OUTPUTS
RESET with PAR/SER = “1” establishes Parallel Outputs active.
tCLKH
tCLKL
tCLK
CLK
Figure 3. CLK Timing Requirements
CLK
IN[15:0]
EXP[2:0]
A/B
tSI
tHI
DATA
Figure 4. Input Data Timing Requirements
CLK
OUT[15:0]
VALID OUTPUT DATA
DVOUT
I/QOUT
tDPR
tDPF
I
Q
I
Q
IA
QA
IB
QB
tDPF
Figure 5. Parallel Output Switching Characteristics
SYNC PULSES: SLAVE OR MASTER
tSY
tHY
CLK
SYNC NCO
SYNC CIC
SYNC RCF
NOTE:
IN THE SLAVE MODE WITH SINGLE CHANNEL OPERATION, THE WIDTH
OF THE SYNC_NCO SHOULD BE ONE SAMPLE CLOCK CYCLE. IN DUAL
CHANNEL MODE, THE PULSEWIDTH SHOULD BE TWO SAMPLE CLOCK
CYCLES. IF A PULSE LONGER THAN SPECIFIED IS USED, THE NCO WILL
BE INHIBITED AND NOT INCREMENT PROPERLY.
Figure 6. SYNC Slave Timing Requirements
CLK
tCHP
tCPL
tCS
tCH
IN[15:0]
E[2:0]
A/B
N+1
N
tCLK
Figure 7. SYNC Master Delay
tRESL
RESET
Figure 8. Reset Timing Requirements


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