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AM1705DPTPA3 数据表(PDF) 6 Page - Texas Instruments

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部件名 AM1705DPTPA3
功能描述  AM1705 ARM Microprocessor
Download  164 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

AM1705DPTPA3 数据表(HTML) 6 Page - Texas Instruments

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AM1705
SPRS657D – FEBRUARY 2010 – REVISED MARCH 2013
www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the changes made to the SPRS657C device-specific data
manual to make it an SPRS657D revision.
Scope: Applicable updates to the AM170x ARM Microprocessor device family, specifically relating to the
AM1705 device, which are all now in the production data (PD) stage of development have been
incorporated.
Revision History
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Updated/Changed Product Status on the 456-MHz Version device from “Advanced Information (AI)” to
Global
“Production Data (PD)”
EMIFA sub-bullet:
Added "NAND (8-Bit-Wide Data)"
Section 1.1
EMIFA sub-bullet:
Features
Updated/Changed “16-Bit SDRAM With 256MB Address Space” to “16-Bit SDRAM With 128MB
Address Space”
Figure 1-1, AM1705 Functional Block Diagram:
Figure 1-1
Functional Block
Added “Memory Protection” in the System Control Block
Diagram
Added figure title
Table 2-1, Characteristics of the Device:
Updated/Changed EMIFB "16-bit , up to 512 Mb SDRAM” to "16-bit, up to 128 MB SDRAM”
Section 2.1
Device
Updated/Changed EMIFA “16bit up 128Mb SDRAM” to “16-Bit up 128 MB SDRAM”
Characteristics
Updated/Changed the JTAG BSDL_ID DEVIDR0 register from “0x9B7D F02F (Silicon Revision 2.0)” to
“0x9B7D F02F (Silicon Revisions 3.0, 2.1, and 2.0)”
Section 2.3.7
ARM Memory
Added “To improve security …” paragraph
Mapping
Table 2-2, AM1705 Top Level Memory Map:
Section 2.4
Updated/Changed “0xC000 0000 - 0xCFFF FFFF” “256M” to “0xC000 0000 - 0xC7FF FFFF” “128M”
Memory Map
EMIFB SDRAM Data
Summary
Updated/Changed “0xD000 0000 - 0xDFFF FFFF” to “0xC800 0000 - 0xDFFF FFFF” "BLANK"
RESERVED row
Updated/Changed section title from "External Memory Interface B (only SDRAM)" to "External Memory
Section 2.6.4
Interface B (SDRAM only)"
External Memory
Interface B (SDRAM
Table 2-6, External Memory Interface B (EMIFB) Terminal Functions:
only)
Updated/Changed EMB_SDCKE, C13, EMIFB SDRAM clock TYPE from “I/O” to “O”
Table 2-19, Reserved and No Connect Terminal Functions:
Section 2.6.17
Reserved and No
Updated/Changed "PWR" to "–" in RSV2 TYPE column
Connect
Added “or left unconnected [do not connect to ground (VSS)].” to RSV3 DESCRIPTION
Table 3-1, System Configuration (SYSCFG) Module Register Access:
Section 3.2
Updated/Changed 0x01C1 4018, DEVIDR0 REGISTER DESCRIPTION from “Device Identification
SYSCFG Module
Register 0” to “JTAG Identification Register
Added 0x01C1 4024, CHIPREVID, Silicon Revision Identification Register row
Section 4.1, Absolute Maximum Ratings Over Operating Junction Temperature Range:
Section 4
Device Operating
Updated/Changed Input voltage ranges, VI I/O, 3.3V (Steady State) from “-0.3V to DVDD + 0.3V” to “-
Conditions
0.3V to DVDD + 0.35V”
Section 4.2, Recommended Operating Conditions:
Updated/Change DVDD, Supply voltage, I/O, 3.3V (DVDD, USB0_VDDA33) MIN value from “3.15” to
“3.0” V
Section 4.3, Notes on Recommended Power-On Hours (POH):
Deleted "Silicon Revision" column in Table 4-1, Recommended Power-On Hours; POH are not silicon
revision dependant
Deleted "300 MHz" Speed Grade row, N/A to this device
Section 5.3.1, Power-On Sequence:
Section 5.3
Power Supplies
Updated/Changed, for clarity, the order the device should be powered-on
6
Contents
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