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ADT7317ARQZ-REEL 数据表(PDF) 11 Page - Analog Devices |
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ADT7317ARQZ-REEL 数据表(HTML) 11 Page - Analog Devices |
11 / 44 page ADT7316/ADT7317/ADT7318 Rev. B | Page 11 of 44 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VOUT-A VREF-AB CS D+ VDD GND VOUT-B VOUT-D VREF-CD SCL/SCLK INT/INT D– LDAC DOUT/ADD SDA/DIN VOUT-C TOP VIEW (Not to Scale) ADT7316/ ADT7317/ ADT7318 Figure 9. Pin Configuration QSOP Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VOUT-B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 2 VOUT-A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 3 VREF-AB Reference Input Pin for DAC A and DAC B. It may be configured as a buffered or unbuffered input to both DAC A and DAC B. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. DAC A and DAC B default on power-up to this pin. 4 CS SPI Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables the input register, and data is transferred in on the rising edges and out on the falling edges of the subsequent serial clocks. It is recommended that this pin be tied high to VDD when operating the serial interface in I2C mode. 5 GND Ground Reference Point for All Circuitry on the Part. Analog and digital ground. 6 VDD Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground. 7 D+ Positive connection to external temperature sensor. 8 D− Negative connection to external temperature sensor. 9 LDAC Active low control input that transfers the contents of the input registers to their respective DAC registers. A falling edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum pulse width of 20 ns must be applied to the LDAC pin to ensure proper loading of a DAC register. This allows simultaneous update of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the LDAC pin. Default is with the LDAC pin controlling the loading of DAC registers. 10 INT/INT Over-Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when temperature or VDD limits are exceeded. Default is active low. Open-drain output—needs a pull-up resistor. 11 DOUT/ADD DOUT: SPI Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on the falling edge of SCLK. Open-drain output—needs a pull-up resistor. ADD: I2C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the address 1001 000, leaving it floating gives the address 1001 010, and setting it high gives the address 1001 011. The I2C address set up by the ADD pin is not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid communication, the serial bus address is latched in. Any subsequent changes on this pin have no affect on the I2C serial bus address. 12 SDA/DIN SDA: I2C Serial Data Input. I2C serial data that is loaded into the device registers is provided on this input. Open- drain configuration—needs a pull-up resistor. DIN: SPI Serial Data Input. Serial data to be loaded into the device registers is provided on this input. Data is clocked into a register on the rising edge of SCLK. Open-drain configuration—needs a pull-up resistor. 13 SCL/SCLK Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of the ADT7316/ADT7317/ADT7318 and also to clock data into any register that can be written to. Open-drain configuration; needs a pull-up resistor. 14 VREF-CD Reference Input Pin for DAC C and DAC D. It can be configured as a buffered or unbuffered input to both DAC C and DAC D. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. DAC C and DAC D default, on power-up, to this pin. 15 VOUT-D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 16 VOUT-C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. |
类似零件编号 - ADT7317ARQZ-REEL |
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类似说明 - ADT7317ARQZ-REEL |
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