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AD9773BSVZRL 数据表(PDF) 2 Page - Analog Devices

部件名 AD9773BSVZRL
功能描述  12-Bit, 160 MSPS, 2x/4x/8x Interpolating Dual TxDAC D/A Converter
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9773BSVZRL 数据表(HTML) 2 Page - Analog Devices

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AD9773
Rev. D | Page 2 of 60
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .......................................................... 1
Table of Contents .............................................................................. 2
Revision History ........................................................................... 2
General Description ......................................................................... 4
Product Highlights ....................................................................... 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
Dynamic Specifications ............................................................... 6
Digital Specifications ................................................................... 7
Digital Filter Specifications ......................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 17
Mode Control (Via SPI Port) .................................................... 18
Register Description................................................................... 20
Functional Description .................................................................. 22
Serial Interface for Register Control ........................................ 22
General Operation of the Serial Interface ............................... 22
Instruction Byte .......................................................................... 23
Serial Interface Port Pin Descriptions ..................................... 23
MSB/LSB Transfers..................................................................... 23
Notes on Serial Port Operation ................................................ 25
DAC Operation........................................................................... 25
1R/2R Mode ................................................................................ 26
Clock Input Configurations ...................................................... 27
Programmable PLL .................................................................... 27
Power Dissipation....................................................................... 29
Sleep/Power-Down Modes........................................................ 29
Two-Port Data Input Mode ...................................................... 30
One-/Two-Port Input Modes.................................................... 30
PLL Enabled, Two-Port Mode .................................................. 30
DATACLK Inversion.................................................................. 31
DATACLK Driver Strength....................................................... 31
PLL Enabled, One-Port Mode .................................................. 31
ONEPORTCLK Inversion......................................................... 31
ONEPORTCLK Driver Strength.............................................. 32
IQ Pairing .................................................................................... 32
PLL Disabled, Two-Port Mode................................................. 32
PLL Disabled, One-Port Mode ................................................. 32
Digital Filter Modes ................................................................... 33
Amplitude Modulation.............................................................. 33
Modulation, No Interpolation .................................................. 34
Modulation, Interpolation = 2× ............................................... 35
Modulation, Interpolation = 4× ............................................... 36
Modulation, Interpolation = 8× ............................................... 37
Zero Stuffing ............................................................................... 38
Interpolating (Complex Mix Mode)........................................ 38
Operations on Complex Signals............................................... 38
Complex Modulation and Image Rejection of Baseband
Signals .......................................................................................... 39
Image Rejection and Sideband Suppression of Modulated
Carriers ........................................................................................ 41
Applying the Output Configurations........................................... 46
Unbuffered Differential Output, Equivalent Circuit ............. 46
Differential Coupling Using a Transformer............................ 46
Differential Coupling Using an Op Amp................................ 47
Interfacing the AD9773 with the AD8345 Quadrature
Modulator.................................................................................... 47
Evaluation Board ............................................................................ 48
Outline Dimensions ....................................................................... 58
Ordering Guide .......................................................................... 58
REVISION HISTORY
10/07—Rev. C to Rev. D
Updated Formatting ........................................................ Universal
Changes to Figure 32 .................................................................... 22
Changes to Figure 108 .................................................................. 54
Updated Outline Dimensions ..................................................... 58
Changes to Ordering Guide......................................................... 58


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