REV. A

AD7709

–9–

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1

IOUT1

Output for Internal Excitation Current Source. Either current source IEXC1, IEXC2, IEXC3, or a combina-

tion of the current sources, can be switched to this output.

2

IOUT2

Output for Internal Excitation Current Source. Either current source IEXC1, IEXC2, IEXC3, or a combina-

tion of the current sources, can be switched to this output.

3

4

5

AIN1

Analog Input. Programmable gain input that can be used as a pseudo-differential input when used with

AINCOM or as the positive input of a fully differential input pair when used with AIN2.

6

AIN2

Analog Input. Programmable gain input that can be used as a pseudo-differential input when used with

AINCOM or as the negative input of a fully differential input pair when used with AIN1.

7

AIN3/P3

Analog Input/Digital Port Bit. Programmable gain input that can be used as a pseudo-differential input when

used with AINCOM or as the positive input of a fully differential input pair when used with AIN4. This pin

can also be programmed as a general-purpose digital input bit.

8

AIN4/P4

Analog Input/Digital Port Bit. Programmable gain input that can be used as a pseudo-differential input when

used with AINCOM or as the negative input of a fully-differential input pair when used with AIN3. This pin

can also be programmed as a general-purpose digital input bit.

9

AINCOM

All analog inputs are referenced to this input when configured in pseudo-differential input mode.

10

11

12

P2/SW2

Dual-Purpose Pin. It can act as a general-purpose output (P2) bit or as a low-side power switch (SW2) to

PWRGND.

13

PWRGND

Ground Point for the Low-Side Power Switches SW2 and SW1. PWRGND must be tied to GND.

14

P1/SW1

Dual-Purpose Pin. It can act as a general-purpose output (P1) bit or as a low-side power switch (SW1) to

PWRGND.

15

RESET

16

SCLK

Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input making

the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted

in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being

SCLK input.

17

CS

Chip Select Input. This is an active low logic input used to select the AD7709.

CS can be used to select the

AD7709 in systems with more than one device on the serial bus or as a frame synchronization signal in com-

municating with the device.

CS can be hardwired low allowing the AD7709 to operate in 3-wire mode with

18

RDY

RDY is a Logic Low Status Output from the AD7709. RDY is low if the ADC has valid data in its data

register. This output returns high on completion of a read operation from the data register. If data is not

read,

RDY will return high prior to the next update indicating to the user that a read operation should

not be initiated.

19

DOUT

Serial Data Output Accessing the Output Shift Register of the AD7709. The output shift register can contain

data from any of the on-chip data or control registers.

20

DIN

Serial Data Input Accessing the Input Shift Register on the AD7709. Data in this shift register is transferred to

the control registers within the ADC, the selection bits of the communications register selecting which

21

GND

Ground Reference Point for the AD7709

22

Supply Voltage, 3 V or 5 V Nominal

23

XTAL2

Output from the 32.768 kHz Crystal Oscillator Inverter

24

XTAL1

Input to the 32.768 kHz Crystal Oscillator Inverter