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DS90UB913ATRTVJQ1 数据表(PDF) 25 Page - Texas Instruments |
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DS90UB913ATRTVJQ1 数据表(HTML) 25 Page - Texas Instruments |
25 / 68 page 1 / fmod FPCLK+ FPCLK- fdev fdev (max) fdev (min) FPCLK Frequency Time 1E+04 JITTER FREQUENCY (Hz) 0.45 1E+05 1E+06 1E+07 0.50 0.55 0.60 0.65 DS90UB913A-Q1, DS90UB914A-Q1 www.ti.com SNLS443A – MAY 2013 – REVISED JUNE 2013 Figure 24. Typical Deserializer Input Jitter Tolerance Curve at 1.4Gbps Line Rate Figure 25. Spread Spectrum Clock Output Profile Table 3. DS90UB913A-Q1 Control Registers Addr Name Bits Field R/W Default Description (Hex) 7-bit address of Serializer; 0x58'h. 7:1 DEVICE ID (0101_100x'b) default. 0xB0'h 0x00 I2C Device ID RW (1011_000) 0: Device ID is from ID[x]. 0 SER ID SEL 1: Register I2C Device ID overrides ID[x]. 7 RSVD Reserved. Digital Output Drive Strength. 6 RDS RW 0 1: High Drive Strength. 0: Low Drive Strength. Auto Voltage Control. 5 VDDIO Control RW 1 1: Enable. 0: Disable. VDDIO Voltage set. 4 VDDIO MODE RW 1 1: VDDIO = 3.3V. 0: VDDIO = 1.8V. This register can be set only through local I2C access. 0x01 Power and Reset 1: Analog power-down. Powers Down the analog block 3 ANAPWDN RW 0 in the Serializer. 0: No effect. 2 RSVD RW 0 Reserved. 1: Resets the digital block except for register values. DIGITAL Does not affect device I2C Bus or Device ID. This bit 1 RW 0 RESET1 is self-clearing. 0: Normal Operation. 1: Digital Reset, resets the entire digital block including DIGITAL 0 RW 1 all register values. This bit is self-clearing. RESET0 0: Normal Operation. 0x02 Reserved. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: DS90UB913A-Q1 DS90UB914A-Q1 |
类似零件编号 - DS90UB913ATRTVJQ1 |
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类似说明 - DS90UB913ATRTVJQ1 |
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