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DS90UB913ATRTVJQ1 数据表(PDF) 38 Page - Texas Instruments

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部件名 DS90UB913ATRTVJQ1
功能描述  DS90UB913A-Q1/DS90UB914A-Q1 25 to100 MHz 10/12-Bit
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DS90UB913ATRTVJQ1 数据表(HTML) 38 Page - Texas Instruments

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DS90UB913A-Q1, DS90UB914A-Q1
SNLS443A – MAY 2013 – REVISED JUNE 2013
www.ti.com
Table 4. DS90UB914A-Q1 Control Registers (continued)
Addr
Name
Bits
Field
R/W
Default
Description
(Hex)
1: Enable Forward Control Channel pass-
through of all I2C accesses to I2C IDs that do
not match the Deserializer I2C ID. The I2C
accesses are then remapped to address
I2C Pass-Through
7
RW
0
specified in register 0x06 (SER ID).
All
0: Enable Forward Control Channel pass-
through only of I2C accesses to I2C IDs
matching either the remote Serializer ID or the
0x21
I2C Control 1
remote I2C IDs.
Internal SDA Hold Time This field configures
the amount of internal hold time provided for
6:4
I2C SDA Hold
RW
0
the SDA input relative to the SCL input. Units
are 50ns.
I2C Glitch Filter Depth This field configures the
3:0
I2C Filter Depth
RW
0
maximum width of glitch pulses on the SCL and
SDA inputs that will be rejected. Units are 10ns.
Control Channel Sequence Error Detected This
bit indicates a sequence error has been
detected in forward control channel.
Forward Channel
7
R
0
1: If this bit is set, an error may have occurred
Sequence Error
in the control channel operation.
0: No forward channel errors have been
detected on the control channel.
Clear Sequence
Clears the Sequence Error Detect bit.
6
RW
0
Error
5
RSVD
Reserved.
SDA Output Delay This field configures output
delay on the SDA output. Setting this value will
increase output delay in units of 50ns. Nominal
output delay values for SCL to SDA are:
4:3
SDA Output Delay
RW
0
00 : ~350ns
01: ~400ns
10: ~450ns
11: ~500ns
Disable Remote Writes to local registers
Setting this bit to a 1 will prevent remote writes
0x22
I2C Control 2
to local device registers from across the control
channel. This prevents writes to the
2
Local Write Disable
RW
0
Deserializer registers from an I2C master
attached to the Serializer. Setting this bit does
not affect remote access to I2C slaves at the
Deserializer.
Speed up I2C Bus Watchdog Timer.
1: Watchdog Timer expires after approximately
I2C Bus Timer
1
RW
0
50µs.
Speedup
0: Watchdog Timer expires after approximately
1s.
Disable I2C Bus Watchdog Timer When the
I2C Watchdog Timer may be used to detect
when the I2C bus is free or hung up following
an invalid termination of a transaction. If SDA is
I2C Bus Timer
0
RW
0
high and no signaling occurs for approximately
Disable
1 second, the I2C bus will assumed to be free.
If SDA is low and no signaling occurs, the
device will attempt to clear the bus by driving 9
clocks on SCL.
General Purpose
Scratch Register.
0x23
7:0
GPCR
RW
0
Control
38
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: DS90UB913A-Q1 DS90UB914A-Q1


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