数据搜索系统,热门电子元器件搜索 |
|
ADC104S101CIMM 数据表(PDF) 2 Page - Texas Instruments |
|
ADC104S101CIMM 数据表(HTML) 2 Page - Texas Instruments |
2 / 27 page IN1 IN4 MUX T/H SCLK VA GND CS DIN DOUT CONTROL LOGIC 10-Bit SUCCESSIVE APPROXIMATION ADC . . . GND ADC104S101 SNAS284F – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Block Diagram Pin Descriptions and Equivalent Circuits Pin No. Pin Name Description ANALOG I/O 4-7 IN1 to IN4 Analog inputs. These signals can range from 0V to VA. DIGITAL I/O 10 SCLK Digital clock input. This clock directly controls the conversion and readout processes. Digital data output. The output samples are clocked out of this pin on falling edges of the 9 DOUT SCLK pin. Digital data input. The ADC104S101's Control Register is loaded through this pin on rising 8 DIN edges of the SCLK pin. Chip select. On the falling edge of CS, a conversion process begins. Conversions continue 1 CS as long as CS is held low. POWER SUPPLY Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and 2 VA bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. 3 GND The ground return for the supply and signals. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC104S101 |
类似零件编号 - ADC104S101CIMM |
|
类似说明 - ADC104S101CIMM |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |