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ADSP-21367KSWZ-2A 数据表(PDF) 10 Page - Analog Devices

部件名 ADSP-21367KSWZ-2A
功能描述  SHARC Processors
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADSP-21367KSWZ-2A 数据表(HTML) 10 Page - Analog Devices

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Rev. E
|
Page 10 of 60
|
July 2009
ADSP-21367/ADSP-21368/ADSP-21369
Peripheral Timers
Three general-purpose timers can generate periodic interrupts
and be independently set to operate in one of three modes:
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watchdog mode
Each general-purpose timer has one bidirectional pin and four
registers that implement its mode of operation: a 6-bit configu-
ration register, a 32-bit count register, a 32-bit period register,
and a 32-bit pulse width register. A single control and status
register enables or disables all three general-purpose timers
independently.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
The TWI master incorporates the following features:
• Simultaneous master and slave operation on multiple
device systems with support for multimaster data
arbitration
• Digital filtering and timed event processing
• 7-bit and 10-bit addressing
• 100 kbps and 400 kbps data rates
• Low interrupt rate
I/O PROCESSOR FEATURES
The I/O processor provides many channels of DMA, and con-
trols the extensive set of peripherals described in the previous
sections.
DMA Controller
The processor’s on-chip DMA controller allows data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously exe-
cuting its program instructions. DMA transfers can occur
between the processor’s internal memory and its serial ports, the
SPI-compatible (serial peripheral interface) ports, the IDP
(input data port), the parallel data acquisition port (PDAP), or
the UART.
Thirty four channels of DMA are available on the ADSP-2136x
processors as shown in Table 6.
Delay Line DMA
The ADSP-21367/ADSP-21368/ADSP-21369 processors pro-
vide delay line DMA functionality. This allows processor reads
and writes to external delay line buffers (in external memory,
SRAM, or SDRAM) with limited core interaction.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory of the processors can be booted up at sys-
tem power-up from an 8-bit EPROM via the external port, an
SPI master or slave, or an internal boot. Booting is determined
by the boot configuration (BOOT_CFG1–0) pins (see Table 7
and the processor hardware reference). Selection of the boot
source is controlled via the SPI as either a master or slave device,
or it can immediately begin executing from ROM.
Power Supplies
The processors have separate power supply connections for the
internal (V
DDINT), external (VDDEXT), and analog (AVDD/AVSS) power
supplies. The internal and analog supplies must meet the 1.3 V
requirement for the 400 MHz device and 1.2 V for the
333 MHz and 266 MHz devices. The external supply must meet
the 3.3 V requirement. All external supply pins must be con-
nected to the same power supply.
Note that the analog supply pin (A
VDD) powers the processor’s
internal clock generator PLL. To produce a stable clock, it is rec-
ommended that PCB designs use an external filter circuit for the
A
VDD pin. Place the filter components as close as possible to the
A
VDD/AVSS pins. For an example circuit, see Figure 3. (A recom-
mended ferrite chip is the muRata BLM18AG102SN1D). To
reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for V
DDINT and GND. Use wide traces
to connect the bypass capacitors to the analog power (A
VDD) and
ground (A
VSS) pins. Note that the AVDD and AVSS pins specified in
Figure 3 are inputs to the processor and not the analog ground
plane on the board—the A
VSS pin should connect directly to dig-
ital ground (GND) at the chip.
Table 6. DMA Channels
Peripheral
DMA Channels
SPORTs
16
PDAP
8
SPI
2
UART
4
External Port
2
Memory-to-Memory
2
Table 7. Boot Mode Selection
BOOT_CFG1–0
Booting Mode
00
SPI Slave Boot
01
SPI Master Boot
10
EPROM/FLASH Boot
11
Reserved


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