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SI5330C-A00207-GM 数据表(PDF) 5 Page - Silicon Laboratories

部件名 SI5330C-A00207-GM
功能描述  Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs
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制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

SI5330C-A00207-GM 数据表(HTML) 5 Page - Silicon Laboratories

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Si5330
Rev. 1.0
5
Table 3. Performance Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
CLKIN Loss of Signal Assert
Time
tLOS
—2.6
5
µs
CLKIN Loss of Signal De-Assert
Time
tLOS_B
After initial start-up time has
expired
0.01
0.2
1
µs
Input-to-Output Propagation
Delay
tPROP
—2.5
4.0
ns
Output-Output Skew
tDSKEW
Outputs at same signal
format
——
100
ps
POR to Output Clock Valid
tSTART
Start-up time for output
clocks
——
2
ms
Table 4. Input and Output Clock Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Input Clock (AC Coupled Differential Input Clocks on Pin IN1/2)
Frequency
fIN
5
710
MHz
Differential Voltage Swing
VPP
710 MHz input
0.4
2.4
VPP
Rise/Fall Time
tR/tF
20%–80%
1.0
ns
Duty Cycle
DC
< 1 ns tr/tf
40
50
60
%
Input Impedance
RIN
10
k
Input Capacitance
CIN
—3.5
pF
Input Clock (DC-Coupled Single-Ended Input Clock on Pin IN3)
Frequency
fIN
CMOS
5
200
MHz
HSTL, SSTL
5
350
MHz
Input Voltage
VI
–0.1
VDD
V
Input Voltage Swing
(CMOS Standard)
200MHz, Tr/Tf= 1.3ns
0.8
Vpp
Rise/Fall Time
tR/tF
20%–80%
4
ns
Duty Cycle
DC
< 2 ns tr/tf
40
50
60
%
Input Capacitance
CIN
—2
pF
Output Clocks (Differential)
Frequency
fOUT
LVPECL, LVDS
5
710
MHz
HCSL
5
250
MHz


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