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74HC74PW 数据表(PDF) 4 Page - NXP Semiconductors |
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74HC74PW 数据表(HTML) 4 Page - NXP Semiconductors |
4 / 21 page 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 — 27 August 2012 4 of 21 NXP Semiconductors 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. [1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Q n+1 = state after the next LOW-to-HIGH CP transition; X = don’t care. 7. Limiting values [1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C. Table 3. Function table[1] Input Output nSD nRD nCP nD nQ nQ L H XXH L H L XXL H L L XXH H Table 4. Function table[1] Input Output nSD nRD nCP nD nQn+1 nQn+1 HH LLH HH HHL Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7 V IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO >VCC +0.5 V - 20 mA IO output current VO = 0.5 V to (VCC +0.5 V) - 25 mA ICC supply current - +100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation DIP14 package [1] - 750 mW SO14, (T)SSOP14 and DHVQFN14 packages [1] - 500 mW |
类似零件编号 - 74HC74PW |
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类似说明 - 74HC74PW |
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