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EPM3064ATC100-5N 数据表(PDF) 35 Page - Altera Corporation

部件名 EPM3064ATC100-5N
功能描述  High–performance, low–cost CMOS EEPROM–based programmable
Download  46 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPM3064ATC100-5N 数据表(HTML) 35 Page - Altera Corporation

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Altera Corporation
35
MAX 3000A Programmable Logic Device Family Data Sheet
tCNT
Minimum global clock
period
(2)
7.9
10.5
ns
fCNT
Maximum internal global
clock frequency
(2), (4)
126.6
95.2
MHz
tACNT
Minimum array clock
period
(2)
7.9
10.5
ns
fACNT
Maximum internal array
clock frequency
(2), (4)
126.6
95.2
MHz
Table 23. EPM3256A Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–7
–10
Min
Max
Min
Max
tIN
Input pad and buffer delay
0.9
1.2
ns
tIO
I/O input pad and buffer delay
0.9
1.2
ns
tSEXP
Shared expander delay
2.8
3.7
ns
tPEXP
Parallel expander delay
0.5
0.6
ns
tLAD
Logic array delay
2.2
2.8
ns
tLAC
Logic control array delay
1.0
1.3
ns
tIOE
Internal output enable delay
0.0
0.0
ns
tOD1
Output buffer and pad delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
1.2
1.6
ns
tOD2
Output buffer and pad delay,
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
1.7
2.1
ns
tOD3
Output buffer and pad delay,
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
6.2
6.6
ns
tZX1
Output buffer enable delay, slow
slew rate = off VCCIO = 3.3 V
C1 = 35 pF
4.0
5.0
ns
tZX2
Output buffer enable delay, slow
slew rate = off VCCIO = 2.5 V
C1 = 35 pF
4.5
5.5
ns
Table 22. EPM3256A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–7
–10
Min
Max
Min
Max


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