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EPM3064ATC100-5N 数据表(PDF) 34 Page - Altera Corporation

部件名 EPM3064ATC100-5N
功能描述  High–performance, low–cost CMOS EEPROM–based programmable
Download  46 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPM3064ATC100-5N 数据表(HTML) 34 Page - Altera Corporation

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Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
tSU
Register setup time
1.4
2.1
2.9
ns
tH
Register hold time
0.6
1.0
1.3
ns
tRD
Register delay
0.8
1.2
1.6
ns
tCOMB
Combinatorial delay
0.5
0.9
1.3
ns
tIC
Array clock delay
1.2
1.7
2.2
ns
tEN
Register enable time
0.7
1.0
1.3
ns
tGLOB
Global control delay
1.1
1.6
2.0
ns
tPRE
Register preset time
1.4
2.0
2.7
ns
tCLR
Register clear time
1.4
2.0
2.7
ns
tPIA
PIA delay
(2)
1.4
2.0
2.6
ns
tLPA
Low–power adder
(5)
4.0
4.0
5.0
ns
Table 22. EPM3256A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–7
–10
Min
Max
Min
Max
tPD1
Input to non–registered
output
C1 = 35 pF (2)
7.5
10
ns
tPD2
I/O input to non–registered
output
C1 = 35 pF (2)
7.5
10
ns
tSU
Global clock setup time
(2)
5.2
6.9
ns
tH
Global clock hold time
(2)
0.0
0.0
ns
tCO1
Global clock to output
delay
C1 = 35 pF
1.0
4.8
1.0
6.4
ns
tCH
Global clock high time
3.0
4.0
ns
tCL
Global clock low time
3.0
4.0
ns
tASU
Array clock setup time
(2)
2.7
3.6
ns
tAH
Array clock hold time
(2)
0.3
0.5
ns
tACO1
Array clock to output delay C1 = 35 pF (2)
1.0
7.3
1.0
9.7
ns
tACH
Array clock high time
3.0
4.0
ns
tACL
Array clock low time
3.0
4.0
ns
tCPPW
Minimum pulse width for
clear and preset
(3)
3.0
4.0
ns
Table 21. EPM3128A Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–5
–7
–10
Min
Max
Min
Max
Min
Max


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