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EPM3064ATC100-5N 数据表(PDF) 31 Page - Altera Corporation

部件名 EPM3064ATC100-5N
功能描述  High–performance, low–cost CMOS EEPROM–based programmable
Download  46 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPM3064ATC100-5N 数据表(HTML) 31 Page - Altera Corporation

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Altera Corporation
31
MAX 3000A Programmable Logic Device Family Data Sheet
Table 19. EPM3064A Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–4
–7
–10
Min
Max
Min
Max
Min
Max
tIN
Input pad and buffer delay
0.6
1.1
1.4
ns
tIO
I/O input pad and buffer
delay
0.6
1.1
1.4
ns
tSEXP
Shared expander delay
1.8
3.0
3.9
ns
tPEXP
Parallel expander delay
0.4
0.7
0.9
ns
tLAD
Logic array delay
1.5
2.5
3.2
ns
tLAC
Logic control array delay
0.6
1.0
1.2
ns
tIOE
Internal output enable delay
0.0
0.0
0.0
ns
tOD1
Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
0.8
1.3
1.8
ns
tOD2
Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
1.3
1.8
2.3
ns
tOD3
Output buffer and pad
delay, slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
5.8
6.3
6.8
ns
tZX1
Output buffer enable delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
4.0
4.0
5.0
ns
tZX2
Output buffer enable delay,
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
4.5
4.5
5.5
ns
tZX3
Output buffer enable delay,
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
9.0
9.0
10.0
ns
tXZ
Output buffer disable delay C1 = 5 pF
4.0
4.0
5.0
ns
tSU
Register setup time
1.3
2.0
2.9
ns
tH
Register hold time
0.6
1.0
1.3
ns
tRD
Register delay
0.7
1.2
1.6
ns
tCOMB
Combinatorial delay
0.6
0.9
1.3
ns
tIC
Array clock delay
1.2
1.9
2.5
ns
tEN
Register enable time
0.6
1.0
1.2
ns
tGLOB
Global control delay
1.0
1.5
2.2
ns
tPRE
Register preset time
1.3
2.1
2.9
ns


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