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EPM7160EQC160-15 数据表(PDF) 31 Page - Altera Corporation

部件名 EPM7160EQC160-15
功能描述  High-performance, EEPROM-based programmable logic devices PLDs) based on second-generation MAX architecture
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPM7160EQC160-15 数据表(HTML) 31 Page - Altera Corporation

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Altera Corporation
31
MAX 7000 Programmable Logic Device Family Data Sheet
Tables 19 through 26 show the MAX 7000 and MAX 7000E AC
operating conditions.
Table 19. MAX 7000 & MAX 7000E External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
-6 Speed Grade
-7 Speed Grade
Unit
Min
Max
Min
Max
tPD1
Input to non-registered output
C1 = 35 pF
6.0
7.5
ns
tPD2
I/O input to non-registered output
C1 = 35 pF
6.0
7.5
ns
tSU
Global clock setup time
5.0
6.0
ns
tH
Global clock hold time
0.0
0.0
ns
tFSU
Global clock setup time of fast input
(2)
2.5
3.0
ns
tFH
Global clock hold time of fast input
(2)
0.5
0.5
ns
tCO1
Global clock to output delay
C1 = 35 pF
4.0
4.5
ns
tCH
Global clock high time
2.5
3.0
ns
tCL
Global clock low time
2.5
3.0
ns
tASU
Array clock setup time
2.5
3.0
ns
tAH
Array clock hold time
2.0
2.0
ns
tACO1
Array clock to output delay
C1 = 35 pF
6.5
7.5
ns
tACH
Array clock high time
3.0
3.0
ns
tACL
Array clock low time
3.0
3.0
ns
tCPPW
Minimum pulse width for clear and
preset
(3)
3.0
3.0
ns
tODH
Output data hold time after clock
C1 = 35 pF (4)
1.0
1.0
ns
tCNT
Minimum global clock period
6.6
8.0
ns
fCNT
Maximum internal global clock
frequency
(5)
151.5
125.0
MHz
tACNT
Minimum array clock period
6.6
8.0
ns
fACNT
Maximum internal array clock
frequency
(5)
151.5
125.0
MHz
fMAX
Maximum clock frequency
(6)
200
166.7
MHz


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