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EPF6016TC100-2 数据表(PDF) 26 Page - Altera Corporation |
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EPF6016TC100-2 数据表(HTML) 26 Page - Altera Corporation |
26 / 52 page 26 Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Figure 15. SameFrame Pin-Out Example Table 6 lists the 3.3-V FLEX 6000 devices with the SameFrame pin-out feature. Output Configuration This section discusses slew-rate control, the MultiVolt I/O interface, power sequencing, and hot-socketing for FLEX 6000 devices. Slew-Rate Control The output buffer in each IOE has an adjustable output slew-rate that can be configured for low-noise or high-speed performance. A slower slew-rate reduces system noise and adds a maximum delay of 6.8 ns. The fast slew-rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew-rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a device-wide basis. The slew-rate setting affects only the falling edge of the output. Designed for 256-Pin FineLine BGA Package Printed Circuit Board 100-Pin FineLine BGA Package (Reduced I/O Count or Logic Requirements) 256-Pin FineLine BGA Package (Increased I/O Count or Logic Requirements) 100-Pin FineLine BGA 256-Pin FineLine BGA Table 6. 3.3-V FLEX 6000 Devices with SameFrame Pin-Outs Device 100-Pin FineLine BGA 256-Pin FineLine BGA EPF6016A vv EPF6024A v |
类似零件编号 - EPF6016TC100-2 |
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类似说明 - EPF6016TC100-2 |
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