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EP4S100G5F45I4 数据表(PDF) 47 Page - Altera Corporation |
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EP4S100G5F45I4 数据表(HTML) 47 Page - Altera Corporation |
47 / 432 page Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–11 Adaptive Logic Modules February 2011 Altera Corporation Stratix IV Device Handbook Volume 1 Extended LUT Mode Use extended LUT mode to implement a specific set of seven-input functions. The set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four inputs. Figure 2–9 shows the template of supported seven-input functions using extended LUT mode. In this mode, if the seven-input function is unregistered, the unused eighth input is available for register packing. Functions that fit into the template shown in Figure 2–9 occur naturally in designs. These functions often appear in designs as “if-else” statements in Verilog HDL or VHDL code. Figure 2–9. Template for Supported Seven-Input Functions in Extended LUT Mode Note to Figure 2–9: (1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available. datae0 combout0 5-Input LUT 5-Input LUT datac dataa datab datad dataf0 datae1 dataf1 DQ To general or local routing To general or local routing reg0 This input is available for register packing. (1) |
类似零件编号 - EP4S100G5F45I4 |
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类似说明 - EP4S100G5F45I4 |
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