EP4S100G4F45I4 datasheet(20/432 Pages) ALTERA

部件名	EP4S100G4F45I4

功能描述	This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Download	432 Pages

Scroll/Zoom	100%

制造商	ALTERA [Altera Corporation]

网页	http://www.altera.com

标志

20 / 432 page

1–6

Chapter 1: Overview for the Stratix IV Device Family

Architecture Features

Stratix IV Device Handbook

September 2012

Altera Corporation

Volume 1

Architecture Features

The Stratix IV device family features are divided into high-speed transceiver features

and FPGA fabric and I/O features.

1 The high-speed transceiver features apply only to Stratix IV GX and Stratix IV GT

devices.

High-Speed Transceiver Features

The following sections describe high-speed transceiver features for Stratix IV GX and

GT devices.

Highest Aggregate Data Bandwidth

Up to 48 full-duplex transceiver channels supporting data rates up to 8.5 Gbps in

Stratix IV GX devices and up to 11.3 Gbps in Stratix IV GT devices.

Wide Range of Protocol Support

Physical layer support for the following serial protocols:

■

Stratix IV GX—PCIe Gen1 and Gen2, GbE, Serial RapidIO, SONET/SDH,

XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, GPON,

SAS/SATA, HyperTransport 1.0 and 3.0, and Interlaken

■

Stratix IV GT—40G/100G Ethernet, SFI-S, Interlaken, SFI-5.1, Serial RapidIO,

SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, 3G-SDI, and Fibre Channel

■

Extremely flexible and easy-to-configure transceiver data path to implement

proprietary protocols

■

PCIe Support

■

Complete PCIe Gen1 and Gen2 protocol stack solution compliant to PCI

Express base specification 2.0 that includes PHY-MAC, Data Link, and

transaction layer circuitry embedded in PCI Express hard IP blocks

f For more information, refer to the PCI Express Compiler User Guide.

■

Root complex and end-point applications

■

x1, x4, and x8 lane configurations

■

PIPE 2.0-compliant interface

■

Embedded circuitry to switch between Gen1 and Gen2 data rates

■

Built-in circuitry for electrical idle generation and detection, receiver detect,

power state transitions, lane reversal, and polarity inversion

■

8B/10B encoder and decoder, receiver synchronization state machine, and

± 300 parts per million (ppm) clock compensation circuitry

■

Transaction layer support for up to two virtual channels (VCs)

类似零件编号 - EP4S100G4F45I4

制造商	部件名	数据表	功能描述
Altera Corporation	EP4SE110	407Kb / 40P	Stratix IV Device
	EP4SE230	407Kb / 40P	Stratix IV Device
	EP4SE230F29I4N	1Mb / 82P	Stratix IV Device Handbook
	EP4SE290	407Kb / 40P	Stratix IV Device
	EP4SE360	407Kb / 40P	Stratix IV Device

More results

类似说明 - EP4S100G4F45I4

制造商	部件名	数据表	功能描述
Altera Corporation	EP3C55F780I7	7Mb / 274P	This section provides a complete overview of all features relating to the Cyclone III device family
NXP Semiconductors	SCF5250EC	1Mb / 56P	This section provides brief descriptions of the features of the SCF5250 processor Rev. 1.3, 07/2006
STMicroelectronics	TN0516	291Kb / 11P	This technical note is an overview of the main features
Altera Corporation	EP2S90F1020C4N	2Mb / 238P	The Stratix II family offers the following features
Freescale Semiconductor...	MCF5272VM66	331Kb / 12P	This document provides an overview of the MCF5272 microprocessor features, including the major functional components.
Altera Corporation	EP3SL70F780C3N	201Kb / 16P	Stratix III Device Family Overview
Infineon Technologies A...	NGC1081	373Kb / 32P	This section provides the pin description of NGC1081. Rev. 1.0 20223-02-16
STMicroelectronics	AN2808	2Mb / 40P	The PM6670S device is a complete
NXP Semiconductors	MC56F826XXDS	1Mb / 60P	The following table is the comparsion of features among members of the family. Rev. 0, 08/2018
Altera Corporation	EP4CE10E22C8N	498Kb / 14P	Cyclone IV FPGA Device Family Overview