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EP4S100G3F35I4 数据表(PDF) 17 Page - Altera Corporation |
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EP4S100G3F35I4 数据表(HTML) 17 Page - Altera Corporation |
17 / 432 page Chapter 1: Overview for the Stratix IV Device Family 1–3 Feature Summary September 2012 Altera Corporation Stratix IV Device Handbook Volume 1 Stratix IV GX Devices Stratix IV GX devices provide up to 48 full-duplex CDR-based transceiver channels per device: ■ Thirty-two out of the 48 transceiver channels have dedicated physical coding sublayer (PCS) and physical medium attachment (PMA) circuitry and support data rates between 600 Mbps and 8.5 Gbps ■ The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbps 1 The actual number of transceiver channels per device varies with device selection. For more information about the exact transceiver count in each device, refer to Table 1–1 on page 1–11. 1 For more information about transceiver architecture, refer to the Transceiver Architecture in Stratix IV Devices chapter. Figure 1–1 shows a high-level Stratix IV GX chip view. Figure 1–1. Stratix IV GX Chip View (1) Note to Figure 1–1: (1) Resource counts vary with device selection, package selection, or both. General Purpose I/O and Memory Interface 600 Mbps-8.5 Gbps CDR-based Transceiver General Purpose I/O and 150 Mbps-1.6 Gbps LVDS interface with DPA and Soft-CDR General Purpose I/O and Memory Interface PLL PLL PLL PLL PLL PLL General Purpose I/O and Memory Interface General Purpose I/O and Memory Interface PLL PLL FPGA Fabric (Logic Elements, DSP, Embedded Memory, Clock Networks) Transceiver Block General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR PLL PLL PLL PLL |
类似零件编号 - EP4S100G3F35I4 |
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类似说明 - EP4S100G3F35I4 |
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