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EP4SE820F35I4 数据表(PDF) 73 Page - Altera Corporation |
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EP4SE820F35I4 数据表(HTML) 73 Page - Altera Corporation |
73 / 432 page Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices 3–17 Clocking Modes December 2011 Altera Corporation Stratix IV Device Handbook Volume 1 ROM Mode All Stratix IV TriMatrix memory blocks support ROM mode. A .mif file initializes the ROM contents of these blocks. The address lines of the ROM are registered on M9K and M144K blocks, but can be unregistered on MLABs. The outputs can be registered or unregistered. Output registers can be asynchronously cleared. The ROM read operation is identical to the read operation in the single-port RAM configuration. FIFO Mode All TriMatrix memory blocks support FIFO mode. MLABs are ideal for designs with many small, shallow FIFO buffers. To implement FIFO buffers in your design, use the Quartus II software FIFO MegaWizard Plug-In Manager. Both single- and dual-clock (asynchronous) FIFO buffers are supported. f For more information about implementing FIFO buffers, refer to the SCFIFO and DCFIFO Megafunctions User Guide. 1 MLABs do not support mixed-width FIFO mode. Clocking Modes Stratix IV TriMatrix memory blocks support the following clocking modes: ■ “Independent Clock Mode” on page 3–18 ■ “Input/Output Clock Mode” on page 3–18 ■ “Read/Write Clock Mode” on page 3–18 ■ “Single Clock Mode” on page 3–18 c Violating the setup or hold time on the memory block address registers could corrupt memory contents. This applies to both read and write operations. Table 3–9 lists which clocking mode/memory mode combinations are supported. Table 3–9. TriMatrix Memory Clock Modes Clocking Mode True Dual-Port Mode Simple Dual-Port Mode Single-Port Mode ROM Mode FIFO Mode Independent Y — — Y — Input/output Y Y Y Y — Read/write — Y — — Y Single clock Y Y Y Y Y |
类似零件编号 - EP4SE820F35I4 |
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