EP4SGX290F35I4 datasheet(41/432 Pages) ALTERA

部件名	EP4SGX290F35I4

功能描述	This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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制造商	ALTERA [Altera Corporation]

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Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices

2–5

Adaptive Logic Modules

February 2011

Altera Corporation

Stratix IV Device Handbook

Volume 1

The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control

signals. The MultiTrack interconnect’s inherent low skew allows clock and control

signal distribution in addition to data.

Adaptive Logic Modules

The ALM is the basic building block of logic in the Stratix IV architecture. It provides

advanced features with efficient logic usage. Each ALM contains a variety of

LUT-based resources that can be divided between two combinational adaptive LUTs

(ALUTs) and two registers. With up to eight inputs for the two combinational ALUTs,

one ALM can implement various combinations of two functions. This adaptability

allows an ALM to be completely backward-compatible with four-input LUT

architectures. One ALM can also implement any function with up to six inputs and

certain seven-input functions.

Figure 2–4. LAB-Wide Control Signals

Dedicated Row LAB Clocks

Local Interconnect

labclk2

syncload

labclkena0

or asyncload

or labpreset

labclk0

labclk1

labclr1

labclkena1

labclkena2

labclr0

synclr

6

There are two unique

clock signals per LAB.

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