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EP4SGX180F35I4 数据表(PDF) 74 Page - Altera Corporation |
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EP4SGX180F35I4 数据表(HTML) 74 Page - Altera Corporation |
74 / 432 page 3–18 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Design Considerations Stratix IV Device Handbook December 2011 Altera Corporation Volume 1 Independent Clock Mode Stratix IV TriMatrix memory blocks can implement independent clock mode for true dual-port memories. In this mode, a separate clock is available for each port (clock A and clock B). Clock A controls all registers on the port A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively. Asynchronous clears are supported only for output latches and output registers on both ports. Input/Output Clock Mode Stratix IV TriMatrix memory blocks can implement input/output clock mode for true dual-port and simple dual-port memories. In this mode, an input clock controls all registers related to the data input to the memory block including data, address, byte enables, read enables, and write enables. An output clock controls the data output registers. Asynchronous clears are available on output latches and output registers only. Read/Write Clock Mode Stratix IV TriMatrix memory blocks can implement read/write clock mode for simple dual-port memories. In this mode, a write clock controls the data-input, write-address, and write-enable registers. Similarly, a read clock controls the data-output, read-address, and read-enable registers. The memory blocks support independent clock enables for both read and write clocks. Asynchronous clears are available on data output latches and registers only. When using read/write clock mode, if you perform a simultaneous read/write to the same address location, the output read data is unknown. If you require the output data to be a known value, use either single-clock mode or input/output clock mode and choose the appropriate read-during-write behavior in the MegaWizard Plug-In Manager. Single Clock Mode Stratix IV TriMatrix memory blocks can implement single-clock mode for true dual-port, simple dual-port, and single-port memories. In this mode, a single clock, together with a clock enable, is used to control all registers of the memory block. Asynchronous clears are available on output latches and output registers only. Design Considerations This section describes guidelines for designing with TriMatrix memory blocks. Selecting TriMatrix Memory Blocks The Quartus II software automatically partitions user-defined memory into embedded memory blocks by taking into account both speed and size constraints placed on your design. For example, the Quartus II software may spread memory out across multiple memory blocks when resources are available to increase the performance of the design. You can manually assign memory to a specific block size using the RAM MegaWizard Plug-In Manager. |
类似零件编号 - EP4SGX180F35I4 |
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类似说明 - EP4SGX180F35I4 |
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