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EP4SE360F35I4 数据表(PDF) 18 Page - Altera Corporation |
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EP4SE360F35I4 数据表(HTML) 18 Page - Altera Corporation |
18 / 432 page 1–4 Chapter 1: Overview for the Stratix IV Device Family Feature Summary Stratix IV Device Handbook September 2012 Altera Corporation Volume 1 Stratix IV E Device Stratix IV E devices provide an excellent solution for applications that do not require high-speed CDR-based transceivers, but are logic, user I/O, or memory intensive. Figure 1–2 shows a high-level Stratix IV E chip view. Figure 1–2. Stratix IV E Chip View (1) Note to Figure 1–2: (1) Resource counts vary with device selection, package selection, or both. General Purpose I/O and Memory Interface General Purpose I/O and 150 Mbps-1.6 Gbps LVDS interface with DPA and Soft-CDR General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR General Purpose I/O and Memory Interface PLL PLL PLL PLL PLL PLL PLL PLL PLL PLL General Purpose I/O and Memory Interface General Purpose I/O and Memory Interface PLL PLL FPGA Fabric (Logic Elements, DSP, Embedded Memory, Clock Networks) General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR |
类似零件编号 - EP4SE360F35I4 |
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类似说明 - EP4SE360F35I4 |
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