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EP4SE360F35I4 数据表(PDF) 86 Page - Altera Corporation |
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EP4SE360F35I4 数据表(HTML) 86 Page - Altera Corporation |
86 / 432 page 4–6 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Simplified DSP Operation Stratix IV Device Handbook February 2011 Altera Corporation Volume 1 To support commonly found FIR-like structures efficiently, a major addition to the DSP block in Stratix IV devices is the ability to propagate the result of one half block to the next half block completely within the DSP block without additional soft logic overhead. This is achieved by the inclusion of a dedicated addition unit and routing that adds the 44-bit result of a previous half block with the 44-bit result of the current block. The 44-bit result is either fed to the next half block or out of the DSP block using the output register stage, as shown in Figure 4–4. Detailed examples are described in later sections. The combination of a fast, low-latency four-multiplier adder unit and the “chained cascade” capability of the output chaining adder provides the optimal FIR and vector multiplication capability. To support single-channel type FIR filters efficiently, you can configure one of the multiplier input’s registers to form a tap delay line input, saving resources and providing higher system performance. Also shown in Figure 4–4 is the optional rounding and saturation unit (RSU). This unit provides a rich set of commonly found arithmetic rounding and saturation functions used in signal processing. In addition to the independent multipliers and sum modes, you can use DSP blocks to perform shift operations. DSP blocks can dynamically switch between logical shift left/right, arithmetic shift left/right, and rotation operation in one clock cycle. Figure 4–4. Output Cascading Feature for FIR Structures 144 44 44 From Previous Half DSP Block To Next Half DSP Block Input Data 44 Half DSP Block Result[] |
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