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EP3C80 数据表(PDF) 83 Page - Altera Corporation |
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EP3C80 数据表(HTML) 83 Page - Altera Corporation |
83 / 274 page Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family 5–23 Phase Shift Implementation July 2012 Altera Corporation Cyclone III Device Handbook Volume 1 Fine resolution phase shifts are implemented by allowing any of the output counters (C[4..0]) or the M counter to use any of the eight phases of the VCO as the reference clock. This allows you to adjust the delay time with a fine resolution. Equation 5–1 shows the minimum delay time that you can insert using this method. For example, if fREF is 100 MHz, N = 1, and M = 8, then fVCO = 800 MHz, and fine = 156.25 ps. The PLL operating frequency defines this phase shift, a value that depends on reference clock frequency and counter settings. Coarse resolution phase shifts are implemented by delaying the start of the counters for a predetermined number of counter clocks. Equation 5–2 shows the coarse phase shift. Equation 5–1. Fine Resolution Phase Shift Note to Equation 5–1: (1) fREF is the input reference clock frequency Equation 5–2. Coarse Resolution Phase Shift Note to Equation 5–2: (1) C is the count value set for the counter delay time—the initial setting in the PLL usage section of the compilation report in the Quartus II software. If the initial value is 1, C – 1 = 0° phase shift. fine TVCO 8 -------------- 1 8fVCO --------------- N 8MfREF ------------------- == = coarse C 1 – fVCO ------------- C 1 – N MfREF ---------------------- == |
类似零件编号 - EP3C80 |
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类似说明 - EP3C80 |
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