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AD9952YSV 数据表(PDF) 5 Page - Analog Devices |
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AD9952YSV 数据表(HTML) 5 Page - Analog Devices |
5 / 28 page AD9952 Rev. B | Page 5 of 28 Parameter Temp Min Typ Max Unit Wake-Up Time6 Full 1 ms Minimum Reset Pulse Width High Full 5 SYSCLK cycles7 I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V Full 4 ns I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V Full 6 ns I/O UPDATE, SYNC_CLK Hold Time Full 0 ns Latency I/O UPDATE to Frequency Change Propagation Delay 25°C 24 SYSCLK cycles I/O UPDATE to Phase Offset Change Propagation Delay 25°C 24 SYSCLK cycles I/O UPDATE to Amplitude Change Propagation Delay 25°C 16 SYSCLK cycles CMOS LOGIC INPUTS Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C 1.25 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C 0.6 V Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C 2.2 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C 0.8 V Logic 1 Current 25°C 3 12 µA Logic 0 Current 25°C 12 µA Input Capacitance 25°C 2 pF CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V Logic 1 Voltage 25°C 1.35 V Logic 0 Voltage 25°C 0.4 V CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V Logic 1 Voltage 25°C 2.8 V Logic 0 Voltage 25°C 0.4 V POWER CONSUMPTION (AVDD = DVDD = 1.8 V) Single-Tone Mode 25°C 162 171 mW Rapid Power-Down Mode 25°C 150 160 mW Full-Sleep Mode 25°C 20 27 mW SYNCHRONIZATION FUNCTION8 Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V) 25°C 62.5 MHz Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V) 25°C 100 MHz SYNC_CLK Alignment Resolution9 25°C ±1 SYSCLK cycles 1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude reduces the phase noise performance of the device. 2 Represents the cycle-to-cycle residual jitter from the comparator alone. 3 Represents the cycle-to-cycle residual jitter from the DDS core driving the comparator. 4 The maximum frequency of the serial I/O port refers to the maximum speed of the port during a write operation. During a register readback, the maximum port speed is restricted to 2 Mbps. 5 Setup time refers to the TCSU (setup time of the falling edge of CS to the SCLK rising edge) and TDSU (setup time of the data change on SDIO to the SCLK rising edge). 6 Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions section). The longest time required is for the reference clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values are used. 7 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency, the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK frequency is the same as the external reference clock frequency. 8 SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2 [11], should be set. 9 This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock edges are aligned, the synchronization function should not increase the skew between the two edges. |
类似零件编号 - AD9952YSV |
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类似说明 - AD9952YSV |
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