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ADV212BBCZRL-150 数据表(PDF) 7 Page - Analog Devices

部件名 ADV212BBCZRL-150
功能描述  Wavescale Video Codec
Download  44 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADV212BBCZRL-150 数据表(HTML) 7 Page - Analog Devices

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ADV212
Rev. B | Page 7 of 44
NORMAL HOST MODE—READ OPERATION
Table 5.
Parameter
Mnemonic
Min
Typ
Max
Unit
RD to ACK, Direct Registers and FIFO Accesses
t
ACK (direct)
1
5
1.5 × JCLK + 7.02
ns
RD to ACK, Indirect Registers
t
ACK (indirect)
1
10.5 JCLK2
15.5 × JCLK + 7.02
ns
Read Access Time, Direct Registers
tDRD (direct)
5
1.5 × JCLK + 7.02
ns
Read Access Time, Indirect Registers
tDRD (indirect)
10.5 JCLK2
15.5 × JCLK + 7.02
ns
Data Hold
tHZRD
2
8.5
ns
CS to RD Setup
tSC
0
ns
Address Setup
tSA
2
ns
CS Hold
tHC
0
ns
Address Hold
tHA
2
ns
Read Inactive Pulse Width
tRH
2.5 JCLK2
ns
Read Active Pulse Width
tRL
2.5 JCLK2
ns
Read Cycle Time, Direct Registers
tRCYC
5.0 JCLK2
ns
1
Timing relationship between ACK falling transition and HDATA valid is not guaranteed. HDATA valid hold time is guaranteed with respect to RD rising transition.
A minimum of three JCLK cycles is recommended between ACK assert and RD deassert.
2
For a definition of JCLK, see Figure 32.
ADDR
tSA
tSC
tHA
tHC
tRL
tACK
tDRD
tHZRD
tRH
tRCYC
HDATA
CS
RD
ACK
VALID
Figure 4. Normal Host Mode—Read Operation


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