H5TQ1G83DFRH9I datasheet(22/34 Pages) HYNIX

部件名	H5TQ1G83DFRH9I

功能描述	1Gb DDR3 SDRAM

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制造商	HYNIX [Hynix Semiconductor]

网页	http://www.skhynix.com/kor/main.do

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Rev. 1.7 /Sep. 2011

22

Table 8 - IDD4W Measurement-Loop Patterna)

a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.

b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.

Table 9 - IDD5B Measurement-Loop Patterna)

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

b) DQ signals are MID-LEVEL.

Datab)

0

WR

0

1

0

1

0

00

0

00000000

1D

1

0

1

0

00

0

-

2,3

D,D

11

1

0

00

0

-

4

WR

0

1

0

1

0

00

0

F

0

00110011

5D

1

0

1

0

00

0

F

0

-

6,7

D,D

11

1

0

00

0

F

0

-

1

8-15

repeat Sub-Loop 0, but BA[2:0] = 1

2

16-23

repeat Sub-Loop 0, but BA[2:0] = 2

3

24-31

repeat Sub-Loop 0, but BA[2:0] = 3

4

32-39

repeat Sub-Loop 0, but BA[2:0] = 4

5

40-47

repeat Sub-Loop 0, but BA[2:0] = 5

6

48-55

repeat Sub-Loop 0, but BA[2:0] = 6

7

56-63

repeat Sub-Loop 0, but BA[2:0] = 7

Datab)

0

REF

0

1

0

-

11.2

D, D

1

0

00

0

-

3,4

D, D

11

1

0

00

0

F

0

-

5...8

repeat cycles 1...4, but BA[2:0] = 1

9...12

repeat cycles 1...4, but BA[2:0] = 2

13...16

repeat cycles 1...4, but BA[2:0] = 3

17...20

repeat cycles 1...4, but BA[2:0] = 4

21...24

repeat cycles 1...4, but BA[2:0] = 5

25...28

repeat cycles 1...4, but BA[2:0] = 6

29...32

repeat cycles 1...4, but BA[2:0] = 7

2

33...nRFC-1

repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.

类似零件编号 - H5TQ1G83DFRH9I

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