H5TQ1G83DFR datasheet(21/34 Pages) HYNIX

部件名	H5TQ1G83DFR

功能描述	1Gb DDR3 SDRAM

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制造商	HYNIX [Hynix Semiconductor]

网页	http://www.skhynix.com/kor/main.do

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21 / 34 page

Rev. 1.7 /Sep. 2011

21

Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.

b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

Datab)

0

RD

0

1

0

1

0

00

0

00000000

1D

1

0

00

0

-

2,3

D,D

11

1

0

00

0

-

4

RD

0

1

0

1

0

00

0

F

0

00110011

5D

1

0

00

0

F

0

-

6,7

D,D

11

1

0

00

0

F

0

-

1

8-15

repeat Sub-Loop 0, but BA[2:0] = 1

2

16-23

repeat Sub-Loop 0, but BA[2:0] = 2

3

24-31

repeat Sub-Loop 0, but BA[2:0] = 3

4

32-39

repeat Sub-Loop 0, but BA[2:0] = 4

5

40-47

repeat Sub-Loop 0, but BA[2:0] = 5

6

48-55

repeat Sub-Loop 0, but BA[2:0] = 6

7

56-63

repeat Sub-Loop 0, but BA[2:0] = 7

类似零件编号 - H5TQ1G83DFR

制造商	部件名	数据表	功能描述
Hynix Semiconductor	H5TQ1G83AFP	4Mb / 77P	1Gb DDR3 SDRAM
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类似说明 - H5TQ1G83DFR

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