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H5PS5182GFRE3L 数据表(PDF) 26 Page - Hynix Semiconductor |
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H5PS5182GFRE3L 数据表(HTML) 26 Page - Hynix Semiconductor |
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26 / 64 page  Rev.1.7 / Feb. 2013 26 H5PS5162GFR series General notes, which may apply for all AC parameters 1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for rising edges and from VIH(dc) and VIL(ac) for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV(250mV to -500 mV for falling egdes). c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe. 2. DDR2 SDRAM AC timing reference load The following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing refer- ence voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown below. 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single VDDQ DUT DQ DQS DQS RDQS RDQS Output VTT = VDDQ/2 25 Timing reference point AC Timing Reference Load VDDQ DUT DQ DQS, DQS RDQS, RDQS Output VTT = VDDQ/2 25 Test point Slew Rate Test Load |
类似零件编号 - H5PS5182GFRE3L |
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类似说明 - H5PS5182GFRE3L |
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