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H5PS5182GFRG7I 数据表(PDF) 51 Page - Hynix Semiconductor |
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H5PS5182GFRG7I 数据表(HTML) 51 Page - Hynix Semiconductor |
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51 / 64 page  Rev.1.7 / Feb. 2013 51 H5PS5162GFR series Specific Notes for dedicated AC parameters 1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet. 2. AL = Additive Latency 3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied. 4. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency 5. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for other slew rate values. 6. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns. See System Derating for other slew rate values. 7. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differen tial slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended mode. See System Derating for other slew rate values. 1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the data- sheet value to the derating value listed in above Table. Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate for line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.) Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value(see Fig.c) △ tDS △ tDH △ tDS △ tDH △ tDS △ tDH △ tDS △ tDH △ tDS △ tDH △ tDS △ tDH △ tDS △ tDH △ tDS △ tDH △ tDS △ tDH 2.0 100 45 100 45 100 45 - - - - - - - - - - - - 1.5 67 21 67 21 67 21 79 33 -- -- -- -- -- 1.0 0 0 0 0 0 0 12 12 24 24 -- -- -- -- 0.9 - - -5 -14 -5 -14 7 -2 19103122 - - - - - - 0.8 -- -- -13 -31 -1 -19 11 -7 23 5 35 17 -- -- 0.7 -- -- -- -10 -42 2 -30 14 -18 26 -6 38 6 -- 0.6 - - - - - - - - -10 -59 2 -47 14 -35 26 -23 38 -11 0.5 -- -- -- -- -- -24 -89 -12 -77 0 -65 12 -53 0.4 -- -- -- -- -- -- -52 -140 -40 -128 -28 -116 DQ Slew rate V/ns DQS, DQS Differential Slew Rate 2.0 V/ns 1.8 V/ns tDS, tDH Derating Values for DDR2-1066(ALL units in 'ps', Note 1 applies to entire Table) 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 4.0 V/ns 3.0 V/ns 0.8 V/ns |
类似零件编号 - H5PS5182GFRG7I |
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类似说明 - H5PS5182GFRG7I |
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