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ISL9N7030BLP3 Datasheet(数据表) 6 Page - Fairchild Semiconductor |
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ISL9N7030BLP3 Datasheet(HTML) 6 Page - Fairchild Semiconductor |
6 page ![]() ©2002 Fairchild Semiconductor Corporation ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA ( oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 19 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RθJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM. Thermal resistances corresponding to other copper areas can be obtained from Figure 19 or by calculation using Equation 2. RθJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads. FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. SWITCHING TIME WAVEFORM Test Circuits and Waveforms (Continued) VGS RL RGS DUT + - VDD VDS VGS tON td(ON) tr 90% 10% VDS 90% 10% tf td(OFF) tOFF 90% 50% 50% 10% PULSE WIDTH VGS 0 0 (EQ. 1) P DM T JM T A – () ZθJA ------------------------------- = (EQ. 2) RθJA 26.51 19.84 0.262 Area + () ---------------------------------------- + = 20 40 60 80 110 0.1 RθJA = 26.51+ 19.84/(0.262+Area) AREA, TOP COPPER AREA (in2) FIGURE 19. THERMAL RESISTANCE vs MOUNTING PAD AREA ISL9N7030BLP3, ISL9N7030BLS3ST |